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Cadence aids ST's 20nm SoC test chip tape-out
Keywords:SoC test chip mixed-signal design flow
[Summary of tips] Cadence Design Systems Inc. announced that it has helped STMicroelectronics' 20nm test chip tape-out. This tape-out marks an industry milestone for Cadence in delivering an end-to-end mixed-signal design flow for 20nm.Engineers from the two companies are said to have collaborated closely to develop technologies and deploy metho......Please login or register with us to view this article>>
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