SPC56xx/RPC56xx MCU family flash memory is comprised of a platform Flash controller interface and two Flash memory arrays.

The PFLASH Controller acts as an interface between the platform’s system bus (AHB Crossbar) and up to two integrated flash memory arrays from STMicroelectronics (90nm for SPC56xx/RPC56xx devices and 5nm for SPC57xx devices).

For SPC57xx devices both banks, code and data, have four buffers. The PFLASH logic associated with the code flash bank contains a four-entry “page” buffer, each entry containing 128bits of data (1 flash page) plus an associated controller which prefetches sequential lines of data from the flash array into the buffer, while the controller logic associated with the data flash bank only supports one 128bit register which serves as a temporary page holding register and does not support any prefetching. Prefetch buffer hits from the code flash bank support zero-wait AHB data phase responses. AHB read requests, which miss the buffers generate the needed flash array access and are forwarded to the AHB upon completion, typically incurring two wait-states at an operating frequency of 60-64MHz.

The Lauterbach Trace32 allows, through an integrated tool, to implement features suited for Context Tracking System (CTS). The implemented CTS algorithms allow the context of the target system to be reconstructed for each single record sampled to the trace buffer. The main application for CTS is the trace-based debugging that allows rerunning of the program and data flow sampled to the trace buffer on the Trace32 screen.

Based on the CTS technology, Trace32 offers the possibility to perform a cache analysis that can be used to emulate and to analyse the flash access.

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