CEVA has developed a communication DSP, the CEVA-XC12, to implement 5G, gigabit LTE, MU-MIMO Wi-Fi and other multi-gigabit modems. Already licensed to a wireless OEM, the CEVA-XC12 delivers up to 8x more efficiency and consumes 50% less power than the CEVA-XC4500 for a 5G baseband modem.

Technologies designed for wireless standards such as 5G will be capable of delivering a peak data rate of up to 20Gbps under 1ms latency. This is achieved by utilising processing techniques such as Massive-MIMO and advanced 3D dynamic beamforming. DSP processors deployed for LTE-Advanced Pro and multi-gigabit wireless standards are incapable of delivering the speed, latency and overall DSP performance required to address the massive technology leap to 5G.

The CEVA-XC12 boasts performance and power efficiency required by multi-gigabit class modems. The processor can be custom configured and scaled to address a range of applications including smartphones and other terminals, advanced and centralised access points, small cells, macro cells and cloud RAN (C-RAN). It supports the full gamut of 5G use cases and deployment scenarios, from 80GHz mmWave down to 450MHz spectrum bands. In addition to 5G, CEVA-XC12 is suited for the design of LTE-Advanced Pro Evolution, enhanced Mobile Broadband (eMBB), Licensed Assisted Access (LAA), MulteFire carrier aggregation and LWA (LTE/Wi-Fi Aggregation), cellular V2X, Wi-Fi 802.11ax, WiGig 802.11ad, Fixed Wireless Access (FWA) and Virtual Reality (VR) systems.

 
CEVA XC12 BD fig1 (cr) Figure 1: The CEVA-XC12 block diagram.  

The CEVA-XC12 DSP architecture features micro-architecture for frequency and power efficiency–capable of operating at 1.8GHz in 10nm and 50% less power than the CEVA-XC4500. The processor boasts computation high bit-rate capabilities–equipped with quad-vector processor engines approaching 1 TOPs performance. The CEVA-XC12 boosts baseband processing components to support 256 and 1024 QAM demodulation, resolution with up to 256 x 256 dimension matrix processing and core streaming interfaces–allowing ultra-low latency transfers between cores or accelerators. The signal processor features control plane for massive-user management and for multi-RAT systems, incorporating a Scalar Processing Unit with a CoreMark/MHz score of 4.4 designed to handle huge number of users required for LTE MTC and 5G IoT.