Imec and EVG have extended their collaboration with an aim to achieve wafer-to-wafer overlay accuracy results in both hybrid bonding and dielectric bonding. EVG will become a partner in Imec’s 3D integration programme through a joint development agreement to further improve overlay accuracy in wafer-to-wafer bonding.

Wafer-to-wafer bonding is a promising technique for enabling high-density integration of future ICs through 3D integration. This is achieved by aligning top and bottom wafers that are then bonded, thus creating a stacked IC. An important advantage is that wafers/ICs with different technologies can be stacked, e.g. memory and processor ICs.

Many of the alignment techniques and bonding methods for 3D integration have evolved from MEMS fabrication methods. The fundamental difference between MEMS and 3D integration is that the alignment or overlay accuracy has to be improved by 5–10 times. Accurate overlay is needed to align the bonding pads of the stacked wafers and it is essential to achieving a high yield with wafer-to-wafer bonding. Imec and EVG have realised excellent results on overlay accuracy.

Firstly, the hybrid (via-middle) wafer-to-wafer bonding technique was improved by using EVG’s bonding system with bonding pads, resulting in a high yield and a 1.8μm pitch that is better compared to recently published results at recognised conferences such as ECTC and 3DIC reporting 3.6μm pad size.

Secondly, the dielectric (via-last) wafer-to-wafer bonding technique was tackled. This technique requires good overlay accuracy to align the copper pads from both wafers that are then contacted by through-silicon vias (TSVs). In this case, 300nm overlay across the wafer was achieved.

 
wafer bonding imec evg stacking 3D body cr Figure 1: Imec improved upon the hybrid (via-middle) wafer-to-wafer bonding technique to get a 1.8µm pitch.  

“Further improving the overlay accuracy for wafer-to-wafer bonding into the sub-200nm range requires optimisation of the interaction between the wafer bonding tool and processes as well as pre-and post-processing and the wafer material,” explained Markus Wimplinger, corporate technology development & IP director at EVG. “We are excited to partner with Imec in an effort to advance overlay accuracies for wafer-to-wafer bonding to meet the needs of future 3D IC designs that rely on high density interconnects.”