The IEEE International Reliability Physics Symposium (IRPS) last week saw IBM discussing an insulator formulation that the company said will help it reach the 7nm node and smaller process geometries. The information was offered during the keynote titled "System Level Reliability Challenges with Technology Scaling," presented by Ronald Newhart, IBM Distinguished Engineer in the IBM Systems & Technology Group (pictured above).

IBM's insulator comes in two forms — silicon-boron-carbon-nitride (SiBCN) and silicon-oxygen-carbon-nitride (SiOCN) — both of which, it said, improve performance and increase yields.

The company also showed how to model line edge roughness (LER) variations filled with SiBCN or SiOCN between wires on a chip as well as new techniques to better measure failure rates by pre-screening chip tests for optimal performance.

In a paper titled "Time Dependent Dielectric Breakdown of SiN, SiBCN and SiOCN Spacer Dielectric," James Stathis, manager of electrical characterization and reliability at IBM Research described how SiBCN and SiOCN outperformed SiN as a spacer dielectric at 10-nanometer thickness (on a 22-nanometer chip) and at six nanometer thickness on a seven nanometer test chip. Its plan is to introduce SiBCN at the 14-nanometer node (already in manufacturing with GlobalFoundries) while SiOCN will being implemented in 7nm. At 5nm IBM hopes to use the ultimate insulator, air gaps, according to Stathis.

Stathis said that accurately modeling how the lifetime of these materials depends on the chip operation voltage is critical, since parasitic capacitance at the advanced nodes is predicted to be as much as 85 percent of the device capacitance when using normal SiN spacers. By using it new materials with a lower dielectric constant (SiBCN and SiOCN) the parasitic capacitance element can be reduced thus improving circuit performance and increasing yields.

 
IBM Power 9 processor (cr) Figure 1: SiBCN and SiOCN have dielectric constants lower than that of SiN used in this Power 9 processor, according to IRPS speaker James Stathis, Manager, Electrical Characterization and Reliability, IBM Research. (Source: IBM)  

LER is also a contributing factor to parasitic capacitance according to two other IBM papers, "A Stochastic Model for the Impact of LER" and "A New and Holistic Modeling Approach for the Impact of Line-Edge Roughness." In them IBM demonstrated how LER results in random variations in the insulator's spacing between wires, adversely affecting dielectric voltage- and time-dependence. Using its holistic stochastic model enabled IBM to make more accurate predictions of the voltage effects on overall chip reliability at advanced nodes.

Engineers from IBM's Fabless Reliability Group were also able to demonstrate how to more accurately predict the dielectric breakdown point of these new insulators using a cognitive computing algorithm. The new "smart" approach, they claimed, drastically improved the efficiency of testing real chips once they are fabricated at the foundry. Their technique achieved optimal pre-screening and test sequencing before a new foundry process was approved.