When designing complex SOCs, most companies deal with third-party processor IP processor. Yet, the processor subsystem verification plays an important role in achieving design goals. The key lies in understanding the effects of instruction execution by the processor (writing the test code with coverage perspective and functional perspective). Let's take a look at the widely used ARM A53 taken as reference for explaining the processor subsystem.

ARM subsystem overview

The figure gives an overview and components associated with our reference processor subsystem. The components shown are generic; you may have additional more AXI interfaces.

GuruprasadFigure1 Figure 1: Processor subsystem and System on Chip is differentiated by different boundary colours (blue denotes the processor subsystem, while pink represents the SoC).

Test bench overview

Here's simple test bench diagram that shows the interface between test bench and the DUT. The test bench performs the functionality of I2C slave, SPI master and Interrupt inputs to interrupt block of DUT. The dotted line C test code to TB memory is about the handshake mechanism that can be achieved.

Guruprasadfigure2 Figure 2: A simple test bench diagram that shows the interface between test bench and the DUT.

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