Selecting a PNR (place and route) tool depends on many factors, like ease of use, run time, ability to handle bigger designs, good optimisation algorithms, closeness to the industry standard signoff and affordability. It is quite common to choose tools across different vendors to suit a given design requirement.

In this event, we are bound to see differences across tools with which we have to tackle many challenges in the design flow. If we end up using a PNR tool which has significant miscorrelation with the signoff STA (static timing analysis) tool, we will need to introduce margins or scaling factors to accommodate the differences. Since the tools use different extraction engines, it is very difficult to derive the margin numbers to apply during PNR optimisation. Additionally, since we have different RC corners, the margins can’t be used flatly across all corners.

The problem

In the advanced technology nodes, the semiconductor design is expected to meet the timing across multiple extraction corners. In a design at our firm, eInfochips, the RC scaling factors used between PNR and the sign-off timing tool were found to be reasonably good for most corners except RC_WC (RC worst case). The RC_WC corner is dominant for nets with longer wire length which have a significant resistance parameter. That is why RC_WC was more pessimistic for setup timing analysis than the C_WC corner and needed additional pessimism to meet the timing. By introducing more pessimism during PNR routing optimisation in terms of resistance scaling, we were able to meet timing at the sign-off stage.

Net delay comparison between RC_WC and C_WC

Long nets are prone to more variation during etching and chemical mechanical polishing processes which cause a reduction in cross-sectional area and increase in resistance.

Figure 1 shows the variation of net delay at two corners (C_WC and RC_WC) for a metal layer5 wire of variable length under 16nm process. At shorter wire lengths (less than 50μm), the net delays are comparable. We can see that as the net length increases, the impact of resistance comes into the picture, increasing the net delay.

einfochips_resscale_01 (cr) Figure 1: Net delay vs. length

Why scale up resistance alone?

As described before, the RC_WC corner already had scaling factors that were not good enough to give decent correlation between PNR and signoff STA. Thus, we wanted to apply extra pessimism only in the RC_WC corner. Most of the violations reported have significant long nets with high resistance. Long nets after fabrication can have variations in thickness which will increase their resistance.

einfochips_resscale_02 (cr) Figure 2: Ideal wire

einfochips_resscale_03 (cr) Figure 3: Fabricated wire

Scaling only resistance is good enough to take care of the resistance effect for long nets. If we scale capacitance also, it will add more pessimism and unnecessary stress on the PNR tool, which could result in over-optimisation and false crosstalk fixes.  
Next: Resistance scaling impacts other design parameters »