To support the development of high-throughput payloads, satellite manufacturers are maximising the benefits of high-speed serial links to connect multiple FPGAs/ASICs on a single PCB and/or transfer data between modules. As bit rates increase, spacecraft OEMs are grappling with how to verify signal integrity and assess the performance and reliability of SERDES channels to ensure sub-systems are developed right-first time.

As high-speed data rates increase and the complexity of links continues to evolve, traditional time-domain SPICE simulation is no longer practical due to extremely long simulation times. Millions of bits are needed to accurately characterise and optimise the performance of SERDES channels.

For those of you who are not familiar with hardware testing of SERDES channels, a Bit-Error Rate Tester (BERT) sends a known data stream such as a PRBS down a link comparing the received waveform with the original. Any differences are noted and using this information, a Bit Error Rate (BER) can be calculated for full, end-to-end performance including the transmitter, the physical medium, and receiver.

The AMI extension to the IBIS specification was developed to simulate a BERT, allow interoperability between models from different semiconductor vendors using commercially available EDA tools, with the ability to simulate ten million bits in minutes. Compared to traditional IBIS, protected, proprietary, behavioural DSP algorithms have been added in the form of compiled executables to support SERDES emphasis and equalisation functions.

IBIS-AMI simulation partitions a link into analog and digital functions with the former comprising the TX/RX buffers, termination, package models and the physical channel. The DSP section includes pre-emphasis, equalisation, and clock/data recovery. The layout of a high-speed serial link between two integrated circuits is shown below which I have annotated to highlight the split.

EEIOL 2016JUN30 Blog1Figure 1: IBIS-AMI's analog (pink) and digital (blue) partitioning of a SERDES link

IBIS-AMI simulation can be used to accurately characterise and optimise the performance of SERDES channels before PCB fabrication, e.g. which connectors to use, the impact of structures, such as vias as well as trace-loss budgets. IBIS-AMI simulation occurs in two stages while preserving the accuracy of transient convolution:

Firstly, the impulse response of the analog section of the link is calculated, comprising the driver, the physical channel, and the receiver.
The impulse response is combined with proprietary models of the TX/RX equalisation and clock recovery to predict overall channel behaviour.

Two types of simulation are supported by the IBIS-AMI standard, statistical and time domain:

Statistical analysis assumes that the TX/RX equalisation is both linear and time invariant and uses the channel's impulse response to quickly compute eye metrics, a bathtub curve, and a BER.
Time-domain simulation allows non-linear and/or time-varying effects in the TX/RX IP, e.g. equalisation, to explore a channel's behaviour in more detail. IBIS-AMI time-domain analysis is fast compared to traditional SPICE, typically processing one million bits in less than a minute.

Early IBIS models contained a simple, lumped-element package model (L_pkg, R_pkg & C_pkg), which only includes self impedance. Later versions allowed an external file for defining RLGC matrices; however, semiconductor vendors now supply broadband, s-parameter package models for SERDES simulation - you must use this option at higher data rates to get the most representative results!

I typically use Mentor's Hyperlynx Boardsim to perform post-layout analyses of SERDES channels between semiconductors accounting for vias, footprints, and traces, and Hyperlynx Linesim to characterise the performance of links between modules including connectors, mating effects, and cables.

As an example, two FPGAs on a single PCB have been connected together using their high-speed serial links. The plots below show the step and impulse responses of the analog channel as well as the received eyes at 1 and 10 Gbps. The presence of vias in the routing of the differential traces is visible in the step and impulse traces.

EEIOL 2016JUN30 Blog2 Figure 2: Characterisation of channel and un-equalised eyes at 1 and 10 Gbps

A second example shows how the received eye of a link between two modules varies as a function of three increasing cable lengths at a bit rate of 10 Gbps.

EEIOL 2016JUN30 Blog3 Figure 3: Unequalised eyes as a function of cable length between two PCBs

For noisy links, IBIS-AMI models allow you to specify parameters such as pre-emphasis and equalisation. Hyperlynx Linesim and Boardsim also enable you to introduce jitter to correlate analysis with actual hardware and offer many different PRBS lengths.

This post has briefly introduced simulating SERDES channels using IBIS-AMI models and if you would like to learn more, this is a topic I teach on my FPGA course. I also demonstrate the Hyperlynx Linesim and Boardsim tools as verification of high-speed serial links has become a major challenge for many satellite OEMs wanting to offer the benefits of high-throughput digital payloads to spacecraft operators.

IBIS-AMI is win-win for everyone: semiconductor vendors, the EDA industry, and spacecraft manufacturers. Simulation is quick and accurate, allowing you to sign-off the development of your sub-systems with confidence and deliver your avionics right-first-time, to cost and schedule.