The new DesignWare High Bandwidth Memory 2 (HBM2) IP platform, consisting of controller, PHY and verification IP, from Synopsys promises to help designers achieve up to 307GB/s aggregate bandwidth, which is 12 times the bandwidth of a DDR4 interface operating at 3200Mb/s data rate.

Built on Synopsys' silicon-proven HBM and DDR4 IP, the complete DesignWare HBM2 provides unique functionality that enables designers to achieve their memory bandwidth, latency and power objectives, according to Synopsys. The DesignWare HBM2 Controller supports pseudo-channel operation in either lock step or memory interleaved mode, allowing users to maximise bandwidth based on their unique traffic pattern.

Both the HBM2 controller and PHY utilise a DFI 4.0-compatible interface to simplify integration with custom DFI-compliant controllers and PHYs.

The DesignWare HBM2 PHY IP offers four trained power management states and fast frequency switching that allows the SoC to manage power consumption by quickly changing between operating frequencies. The DesignWare HBM2 PHY enables a microbump array that matches the JEDEC HBM2 SDRAM standard for the shortest possible 2.5D package routes and highest signal integrity. To simplify HBM2 SDRAM testing, the DesignWare HBM2 PHY IP provides an IEEE 1500 port with an access loopback mode for testing and training the link between the SoC and HBM2 SDRAM.

20170731_EETI_Synopsys-designware-hbm2-block (cr) Figure 1: DesignWare HBM2 block diagram. (Source: Synopsys)

Synopsys VC Verification IP for HBM is fully compliant to HBM JEDEC specification, including HBM2, and provides protocol, methodology, verification and productivity features including built-in protocol checks, coverage and verification plans, as well as Verdi protocol-aware debug and performance analysis, enabling users to achieve rapid verification of HBM-based designs.

The DesignWare HBM2 PHY and VC Verification IP are available now for 14nm and 7nm process technologies, with additional process technologies in development.