USB-IF's TDB.220.127.116.11 lists 18 specific assertions that must be checked for each power transition.
The key assertions covered in this test are shown in Table 2 and include tSrcSettlePos, which mandates that the Source reach the new voltage within 275 ms. The Slew Rate from the power source is also checked should not exceed 30 mV/µs. Once VBUS is within 20% of the target voltage, it should not fall below this level again. Finally, once the DUT issues the PS-READY indicating it has reached the new power level, the load box draws the requested current at a rate of 100 mA per μs and the DUT must stay within 0.5 V of vSrcNew for the next 80 ms.
*__Table 2:__ Key Power Delivery timing and power measurements for power transitions. Source: USB Power Delivery 2.0 Release 1.2 Specifications.*
This final stage of the TDB.18.104.22.168 is shown in Figure 4, which illustrates how PD Compliance frequently requires correlating logical protocol messages with VBUS power measurements. In the power graph, the vertical blue line is positioned on the PS-READY and the dotted line identifies where the load box initiate’s its current draw (current is shown as a negative value in the graphical display because it moves in the opposite direction of voltage). Some initial droop in the source VBUS voltage is also observed and this ringing waveform effect may be caused by a switching regulator on the power supply.
The zoomed area in Fig. 4 shows where the initial current draw kicks on. This is where most problems are seen (low cost power supplies often exhibit voltage droop once the load is applied. This is OK but it needs to remain within 0.5 V of agreed power level).
*__Figure 4:__ The PD Compliance capture log above shows the final stage of TDB.22.214.171.124 where the load box initiates its current draw causing substantial droop in VBUS voltage. The observable ringing waveform effect is typically associated with a switching regulator on the power source.*
While the PD initiative started with a modest goal of faster VBUS charging, it has evolved into one of the most ambitious USB initiatives in recent memory. Migrating from a legacy VBUS architecture to the more sophisticated policy-based Power Delivery design has PD OEMs working overtime to gain compliance. This brief article addresses only a handful of key assertions in a test spec that includes over 400 individual test points.
As the industry moves from PD chipset to end-product certification, OEMs are using a range of optional features to tailor their offering for specific applications further complicating the test procedure. For PD test equipment vendors, correlating logical protocol state changes with precise power measurements has been the key challenge. Now that the official test specifications have been finalized, the success of USB PD will depend on the industry's continued focus on delivering compliance and interoperability.