NRAM Roadmap Emerges

Article By : Rick Merritt

Carbon nanotube based memory incoming next year, and it's compatible with existing controllers

CUPERTINO, Calif. — Nantero made its case at Hot Chips here that its design based on carbon nanotubes (CNTs) is poised to become a replacement for DRAM. As a first step, partner Fujitsu aims to ship next year a DDR4 DRAM alternative using the technology.

DRAM represents the largest sector of the semiconductor market, expected to surpass $100 billion in sales this year in part thanks to spiking prices. The technology behind it is expected to hit a wall around the 64-Gbit device, driving suppliers such as Micron to explore alternatives such as phase-change memories.

Nantero’s non-volatile NRAMs use electrostatic charge to activate systolic arrays of CNT cells it claims are relatively easy to sputter on to any CMOS process. It claims it will outstrip the DRAM roadmap starting with stacks of 4-Gbit, 100mm2 die made in a 28nm process into initial 8- and 16-Gbit chips.

“That’s not a bad start — it’s a market in itself,” said Bill Gervasi, principal chief architect for Nantero.

Theoretically, DDR4 supports up to eight-layer stacks, DDR5 handles 16 and future processes may allow denser individual layers. Nantero forecasts a 64 Gbit NRAM could be made in a 14nm process and a 256-Gbit device in 7nm, both using four layers.

Nantero created a DDR4 reference design “to get the technology moving…this is scalable way beyond DRAM, so I think we have a comfortable road map to replace DRAM,” Gervasi said.

In a Q&A, attendees tried to poke holes in the approach but opened no glaring gaps. “I lose sleep every night wondering when another shoe will drop, but we have built thousands of test chips, though not a 16-Gbit device. Our customers will do that,” Gervasi said.

The CNT cells exhibit some variations from standard DRAM timing. However, they should work with unmodified DRAM controllers and deliver read/write speeds down to 5 nanoseconds and 5 femtojoules/bit, within the power envelop of DRAM DIMMs, he said.

“Customers say they will handle encryption on the processor side” to deal with the non-volatile nature of the main memory, he said. He noted work over the last several years to build support for non-volatile main memory in Windows, Linux and apps.

NRAM timing with ECC differs from DRAMs but it can still use existing controllers. (Image: Nantero)

NRAM timing with ECC differs from DRAMs but it can still use existing controllers. (Image: Nantero)

Regarding soft errors, “these devices have been sent into space and we have data on temperature, alpha and gamma rays — there’s nothing you can do with a CNT to get it to do something weird,” he said.

Part of Nantero’s secret sauce is in the slurry used to form the CNTs and details of the device size and shape. “We design and build equipment at the vendor’s site,” he said. The company also has proprietary technology on how to direct electrostatic signals for reads and writes.

The company announced in April it secured of $29.7 million from eight investors including DIMM-maker Kingston and the investment divisions of Dell, Cisco and China’s leading foundry, SMIC.

— Rick Merritt, Silicon Valley Bureau Chief, EE Times

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