Macronix Aiming to Cut NAND Prices

Article By : Rick Merritt

Belives it can shave a third off the current price levels

CUPERTINO, Calif. — Miin Wu believes that he can cut 3D NAND prices by a third. The founder of Macronix is raising funds for a three-year effort that is both ambitious and pragmatic.

The NOR and ROM maker seeks funds to expand by a little more than 10% of its current capacity of about 400,000 12-inch equivalent wafers/month. An extra 50,000 wafers/month will initially be in traditional 3D NAND. Once it establishes a customer base, it will ramp a novel architecture that it claims sports 30% lower cost per bit.

If all goes well, the company aims to release its first chips in in a little more than two years. Miin Wu was in Silicon Valley recently to discuss with equipment makers details of key etch tools needed to make competitive 3D NAND parts.

Miin Wu

“Right now, all my R&D money is spent on 3D NAND,” said Miin Wu, noting that he expects to make his own controllers, too. “If I can build a 50,000-wafer capacity, I can compete and make money, but for our full ROI, we need multiples of that, so we will need to expand.”

Macronix is not the only wannabe in the burgeoning market for 3D NAND. China’s Yangtze Memory Technology Co. aims to deliver 256-Gbit chips late next year supporting data rates up to 3.0 Gbits/s using a proprietary Xstacking technology. YMTC was founded in 2016 with a whopping $24 billion in funding, leveraging the 12-inch fabs of China’s XMC in Wuhan.

YMTC plans to be in volume production of conventional 32-layer NAND chips by October. If all goes well, in a little more than a year, it could be producing chips at a rate of 100,000 wafers/month in the first phase of a new fab with a second phase planned to triple capacity, fueling plans to take 10% to 20% of the worldwide NAND market.

It’s a big, risky bet to gain a position in a highly competitive field. Just last month, SK Hynix announced that it will sample before the end of the year a 512-Gbit version of its 96-layer chips and a Tbit version before June. Larger rivals Samsung and Toshiba are already shipping similar parts today. The top vendors, which include Micron, are said to be well on their way to cracking the 100-layer level with plans extending to hundreds of levels.

Despite the heady competition, Macronix “has a good opportunity to focus on lower-density parts that major vendors obsolete — in a shortage, that’s a great place to be,” said analyst Jim Handy of Objective Analysis, who estimates that the flash market will hit $58 billion this year, up 23% over 2017.

That’s the kind of position in trailing-edge memories that Macronix has traditionally pursued. This time around, however, Miin Wu said that he aims to deliver 3D NAND parts at the same density but lower costs as rivals.

Handy said that the goal would challenge the Taiwan company’s business model that, to date, has focused more on high-mix, low-volume products. Success will also depend on the state of NAND ASPs, which have been declining from 27 cents/GByte to 20 cents/GB, noted Handy.

“I believe that memory can be the other strength of Taiwan,” said Miin Wu, who founded Macronix in 1989, when TSMC was just two years old.

Today, TSMC is producing state-of-the-art SoCs at 7 nm, while Macronix is best-known as a leader in older memory products such as NOR flash and ROMs made in 90- and 35-nm nodes. That said, Macronix has its share of innovations with more than 7,600 patents, said Miin Wu, who helped design the EEPROM while at Intel in the 1970s.

Macronix plans a number of stops along the way to its 3D NAND dreams. It plans to sample 4-GByte eMMC NAND by the end of the year. It’s also driving NOR down to 1.2 V for low-power IoT chips with standby power measured in nanoamps.

Nintendo remains its largest customer overall. In China, Huawei is its largest customer and likely one of the first to use its eMMC chips in products such as base stations.

— Rick Merritt, Silicon Valley Bureau Chief, EE Times

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