The core supports up to six Base Address Registers and Expansion ROM address register with both I/O and memory space decoding up to 4GB.
The DTPCI32DC from SoC design house Digital Core Design is a 32-bit target interface which meets all requirements of the PCI 3.0 specification for a target device. It compromises a minimal gate count with a high-bandwidth data transfer.
The core’s main feature is the presence of two clock domains, which enable flexibility and higher performance, said Tomek Krzyzak, VCEO of Digital Core Dresign, adding that when the time required for implementation becomes crucial, the DTPCI32DC brings a domain crossing. Saved time can be used for a specific system implementation instead. The user-friendly back-end interface can be very easily and effectively tailoured to the design needs.
The core supports up to six Base Address Registers and Expansion ROM address register with both I/O and memory space decoding from 16bytes up to 4GB. Another important feature is a cache wrapping hardware support and a cacheline pre-fetching capability.
The DTPCI32DC is accepting size cache lines which are powered from 2 up to 128. It enables also target-disconnect with data, without data or by a target abort. The DTPCI32DC is capable to work with 66MHz clock frequency in the most popular technologies. It assures the PCI timing requirements, as well as other parameters like FIFOs depths number or Base Address Registers, which can be easily configured at the pre-synthesis stage.
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