3D DRAM on the Horizon

Article By : Gary Hilson

DRAM is heading toward 3D, which will require new manufacturing equipment and materials.

It may take a few years, but DRAM is likely to follow the footsteps of NAND and go 3D, which means it will need new manufacturing equipment and materials to do it cost-effectively.

Applied Materials’ latest materials engineering solutions are all about supporting DRAM scaling in the near term and positioning customers for the longer term. Aimed at accelerating improvements in chip performance, power, area, cost, and time to market, the company’s new offerings target three areas of DRAM chips: storage capacitors, interconnect wiring, and logic transistors.

Applied Materials’ Draco is a new hard mask material that has been co-optimized to work with the company’s Sym3 Y etch system in a process monitored by its PROVision eBeam metrology and inspection system. It can take nearly half a million measurements per hour, said Sony Varghese, director of strategic marketing for the company’s memory, semiconductor products group. This new material increases etch selectivity by more than 30%, which enables a shorter mask. The combination of Draco and the Sym3 Y etch system uses advanced RF pulsing to synchronize etching with by-product removal to enable patterning holes that are perfectly cylindrical, straight, and uniform, he said.

Sony Varghese

The PROVision eBeam system enables capacitor uniformity by providing customers with immediate and actionable data on hard mask critical dimension uniformity as to reduce bridge defects. By reducing defects, customers can increase yields. “What we need is a material that won’t etch as fast under the aggressive etch conditions,” Varghese said Applied Material’s new hard mask material offers greater etch selectivity.

Draco addresses a critical challenge that is a result of decreased cell area and decreased capacitor diameters when high k dielectric material is deposited between two thin metal electrodes to form a parallel plate capacitor. As the cell area decreases, the diameter of the capacitor decreases as well, he said. “The aspect ratio, which is the ratio of the height of the capacitor to its diameter, has been decreasing node over node. As the hole diameter gets narrower it gets more challenging to etch the deep holes and effectively remove the by-products.”

In addition, said Varghese, etch ion energies are increasing to maintain a steady etch rate, and the change in the process leads to hard mask material getting etched away before the full hole is fully formed. “Increasing the thickness of the hard mark only makes the aspect ratio worse and gets to a point of diminishing returns, he said. “Defects and variations in the dimensions of the capacitor also get worse because of these challenges.” By using Draco, customers have been able to reduce the thickness of the hard mark by 30%. “The quality of the holes made in the hard mark has to have the best uniformity and shape as possible since any distortions in it would transfer to the next mold etch process.”

Applied Materials is also addressing the challenges created by continual thinning of the dielectric layers that have enabled reduced DRAM die sizes. Because the dielectrics are now too thin to prevent capacitive coupling in the metal lines, signals are prone to interfere with one another causing higher power consumption, slower performance, increased heat, and reliability risks. Rather than use one of two silicon oxides (silane and tetraethoxysilane) as the dielectric material, Varghese said the solution is bringing Applied Materials’ Black Diamond low-k dielectric to the DRAM market. First used in advanced logic, the company has adapted it for use with its Producer GT platform. “Black Diamond offers a 25% reduction in dielectric constant compared to the current Silicon oxide films.” He said it also enables smaller, more compact interconnect wires that can move signals through the chips at multi-gigahertz speeds without interference and at lower power consumption.

DRAM manufacturers are finding that the increasing costs of patterning, as well as possibly hitting limits of physics, make scaling in the two dimensions more challenging. (Image source: Applied Materials)

The third area Applied Materials is targeting is the performance, power, area, and cost of the transistors used in the periphery logic of the chip to help drive the input-output (I/O) operations needed in high-performance DRAM such as those based on the new DDR5 specification. The expectation is that over time, high-k metal gate (HKMG) transistors will replace polysilicon transistors in DRAM, just as they did in logic, to improve gate capacitance, leakage, and performance.

Moving to a HKMG materials stack does create its own set of challenges for manufacturing because it’s more complex and delicate, which Applied Materials is addressing with its Endura Avenir RFPVD system for in-vacuum processing of adjacent steps. The company’s epitaxial deposition technologies, combined with several different film treatment options, are also being used by customers to fine-tune the HKMG transistor characteristics for optimum performance, said Varghese.

This article was originally published on EE Times Europe.

Gary Hilson is a freelance writer and editor who has written thousands of words for print and pixel publications across North America. His areas of interest include software, enterprise and networking technology, research and education, sustainable transportation, and community news. His articles have been published by Network Computing, InformationWeek, Computing Canada, Computer Dealer News, Toronto Business Times, Strategy Magazine, and the Ottawa Citizen.

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