8-channel XMC module targets phased array radar

Article By : Pentek

The module’s built-in data capture offers a turnkey solution as well as a platform for developing and deploying custom FPGA-processing IP.

Pentek has expanded its Jade lineup with Model 71131 XMC modules based on the Xilinx Kintex UltraScale FPGA. The Model 71131 is an eight-channel, 250MHz module featuring 16bit ADCs with programmable multiband digital down converters (DDCs).

The Model 71131 is suitable for HF or IF ports of a communications or radar system with its’ built-in data capture that offers a turnkey solution as well as a platform for developing and deploying custom FPGA-processing IP. The eight channels are beneficial for multi-channel phased array platforms in defence and weather radar applications where the cost per channel can be reduced.

The front end accepts eight analog HF or IF inputs on front panel MMCX connectors with transformer coupling into four Texas Instruments’ ADS42LB69 dual 250MHz, 16bit A/D converters. The digital outputs are delivered into the Kintex UltraScale FPGA for signal-processing and routing to other module resources.

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Figure 1: The Model 71131 also has eight A/D acquisition IP modules for easy capturing and moving of data.

Each IP module can receive data from any of the eight A/Ds or a test signal generator. Powerful linked-list DMA engines move the A/D data through the PCIe interface in a unique acquisition gate driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior to data acquisition; rather, it is governed by the length of the acquisition gate. This is useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely to vary.

Within each A/D acquisition IP module is a DDC IP core. Because of the flexible input routing of the A/D acquisition IP modules, many different configurations can be achieved, including one ADC driving all eight DDCs or each of the eight ADCs driving its own DDC.

Each DDC has an independent 32bit tuning frequency setting from DC to the A/D sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as eight different output bandwidths. Decimations can be programmed from 2 to 32,768, delivering bandwidths from 100MHz down to a few kHz.

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