Server segments are driving significantly higher performance requirements from memory subsystems.
TORONTO — Micron Technology chose CES 2020 to unveil its DDR5 chip, which is ironic, since the latest iteration of DRAM will initially find the most demand from data center applications before popping up in client devices.
In amongst giant wall-mounted LEDs, smartphones, and “impossible pork,” Micron announced it had begun sampling its DDR5 Registered DIMMs based on its industry-leading 1znm process technology. Director of data center marketing Ryan Baxter told EE Times in a recent telephone interview that because DDR5 doubles memory density, it will feed the need in data centers for growing processor core counts with increased memory bandwidth and capacity. However, it will be nine months to a year before sampling will begin in large quantities to a wide variety of customers, he said.
“Mainstream customer sampling begins the latter part of 2020, in preparation for a ramp that’s going to occur right around about a year from now,” Baxter said.
DDR5 adoption is expected to be driven primarily by the enterprise and cloud space server segments, according to Baxter. “The next generation CPUs are going to need a whole lot more memory performance to be able to be optimized for what the customers are typically using CPUs for these days.”
Client adoption will follow, he said, but how a new DRAM spec gets traction has changed in the last three or four years when clients such as PCs were a massive part of the overall DRAM demand envelope. “They’re still big, but cloud and enterprise essentially have surpassed clients in terms of the size of the demand for DRAM these days.”
The client market has become quite diverse, said Baxter, as it encompasses a variety of devices, including traditional desktops and laptops, tablets and smartphones, some of which will take the LPDDR flavor. Certain user segments are going to want the performance bump that comes with DDR5 immediately, such as avid gamers, while price conscious users will be content with DDR4 for longer. The mobile space will vary too. “You have this fragmentation happening in the client space that will likely be a combination.”
But in the shorter term, it’s the server side that will consume DDR5 first, said Baxter, as the enterprise and cloud server segments are both driving significantly higher performance requirements from its memory subsystems and core counts grow at an unprecedented pace from 10-15 % year-on-year in the recent past to a predicted 25% over the next four or five years.
An example of a scenario that is fueling this core count demand is Amazon Web Services and Azure offering virtual machines in the form of cloud services, he said. “What DDR5 provides is significantly better performance out of the memory subsystem. Again, that’s craved by the multi-core CPU. We’re looking at dozens of cores per single piece of silicon.”
It helps that the transition from DDR4 to DDR5 represents far more than a typical generational change in that it has overhauled the DDR architecture and set a higher bar for overall performance. For example, a comparison of DDR4 and DDR5 bandwidths at DDR4’s maximum data rate, 3200MT/s, in a system-level simulation shows DDR5 has a 1.36-times increase in effective bandwidth, and DDR5 is expected to grow system bandwidth greater than double its current state, driven by increased data rates, as well as overall architectural changes.
The new DDR5 chip built using Micron’s 1Z nanometer process, and it’s technically the third part at 1Z, said Baxter, including a DDR4 and LPDDR4 part, as the company wanted to ramp up DDR5 on a process that was fully optimized.
Putting out a DDR5 part on a 1Znm process likely puts Micron in a leading position as a DRAM maker, according to Jim Handy, principal analyst with Objective Analysis, with the company having fallen behind in process migration back in 2016. It comes at a time when DRAM prices have hit significant lows, he said, so it makes sense to move to 1Z as much as possible as it’s cheaper, and may allow Micron to eke out a small profit margin until prices swing back up.
As for where DDR5 will end up first, Handy said it’s following in DDR4’s footsteps in hitting the data center first, whereas previous iterations were all adopted in PCs first. Aside from the server performance requirements, he chalks it up to the influential Intel shifting its focus from the PC market as it realizes its profitability in server products is a whole lot stronger, which means technical advances will trickle down to the PC.
Aside from this flip in demand segments, DDR5 is on schedule from a roadmap perspective, and will likely see similar longevity to that of its predecessor, said Handy. Outside of the data center, one will be to support the increasing amount of graphics in a lot of different end-user experiences, he said. “The other one is artificial intelligence, but although it’s used in the hyper scale data centers a good bit, it hasn’t really found its way into the everyday life of people yet.”
Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.