Synopsys’ DesignWare ARC HS38 processor, DDR4 and PCI Express 3.1 IP offer high performance at low power consumption for Starblaze’s SSD controller.
Starblaze has achieved first-pass silicon success for its MB1000 enterprise SSD controller using Synopsys' DesignWare ARC HS38 processor as well as DDR4 and PCI Express controller and PHY IP.
According to Synopsys, Starblaze selected the ARC HS38 processor because it offers multicore support for SMP Linux, a 40bit physical address space and the ARC Processor EXtension (APEX) technology that enabled them to add instructions to reduce I/O latency. Furthermore, the ARC HS38 processor offers higher performance at half the power consumption. Starblaze also selected DesignWare DDR4 and PCI Express 3.1 IP to meet their performance requirements and deliver a differentiated, production-ready design within a tight time-to-market schedule.
Starblaze selected the DesignWare DDR4 IP to enable efficient memory access in its storage applications. The IP supports high-capacity DDR4 and DDR4 3D stacked (DDR4-3DS) DRAM with 16 ranks of memory to expand capacity by up to 400% compared to the previously supported four ranks, without reducing performance. Starblaze also integrated the DesignWare IP for PCI Express 3.1 that delivers 98% throughput efficiency with low latency. The DesignWare IP for PCI Express 3.1 supports PCI-SIG Single Root I/O Virtualisation (SR-IOV) technology that enables the simultaneous sharing of peripherals across multiple CPUs or operating systems. Both the DesignWare DDR4 and PCI Express 3.1 IP include reliability, availability and serviceability (RAS) features to increase data protection, system availability and issue diagnosis for high-performance, data-intensive applications such as enterprise SSDs.
Figure 1: Starblaze MB1000 SSD Controller's performance results at the near-end with DesignWare IP shows clear eyes and wide margins.
To get their new-generation PCI Express-based MB1000 SSD to production quickly, Starblaze selected Synopsys' DesignWare ARC HS38 processor and MetaWare Development Toolkit. The ARC HS38 processor's pipeline and instruction set architecture (ISA) include features that enabled Starblaze to achieve the high I/O operations per second required to meet their design goals. Speculative instruction execution in the processor increases instruction-level parallelism by allowing subsequent instructions to propagate through the pipeline even before current instructions have retired.
In addition, the ARC HS38 processor has single-cycle load-to-use latencies for many instructions due to internal forwarding paths and a late ALU stage in the 10-stage pipeline, reducing stalls and yielding higher efficiency in the program flow. The ARC HS38 processor also has load and store queues that support multiple outstanding memory transactions, and support 64bit loads and stores and non-aligned load/store accesses, without extra cycle penalties, so blocks of data can be moved efficiently.