Cadence PHY and Controller IP in TSMC N7, N6 and N5 Process Nodes Achieves PCIe 5.0 Compliance

Article By : Cadence Design Systems Inc.

Cadence's PHY and Controller IP for PCIe 5.0 specification in the TSMC N7, N6 and N5 process technologies have passed certification tests.

Cadence Design Systems Inc.’s PHY and Controller IP for the PCI Express (PCIe) 5.0 specification in the TSMC N7, N6 and N5 process technologies have passed certification tests from PCI-SIG at the industry’s first event for PCIe 5.0 specification compliance held in April.

The Cadence solutions were tested to their full potential and complied with the full speed of 32GT/s for PCIe 5.0 technology. The compliance program provides designers with testing procedures to assess that the PCIe 5.0 interfaces on their system-on-chip (SoC) designs will operate as expected.

The Cadence IP for PCIe 5.0 technology consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications. With Cadence’s PHY and Controller Subsystem for PCIe 5.0 architecture, customers can design extremely power-efficient SoCs while accelerating time to market.

“We are pleased Cadence has certified its comprehensive IP family for compliance with the PCIe 5.0 protocol on TSMC’s advanced processes,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “Our continued close collaboration with Cadence is helping our mutual customers meet the stringent power and performance requirements and accelerate silicon innovation with leading-edge design solutions benefiting from TSMC’s advanced technologies.”

“With the lowest power consumption in the market as validated by our customers, Cadence’s certified PHY and Controller IP for PCIe 5.0 enables them to develop extremely power-efficient SoCs,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “With our multi-lane subsystem-on-a-chip solution, our customers can see IP compliance being achieved in form factors that match their target applications.”

“Consistent with previous testing, Cadence’s PHY and controller test chips for the PCIe 5.0 specification showed robust performance in compliance tests on our Xgig exerciser and analyzer platform,” said Tom Fawcett, senior vice president and general manager, Lab & Production Business Unit, VIAVI Solutions. “Cadence is at the leading edge of high-bandwidth hyperscale SoC IP, and their successful track record in PCI-SIG compliance events should project continued confidence in their solutions and the technology as a whole.”

“Intel is dedicated to industry-wide innovation and rigorous compatibility testing through the open PCI Express standard,” said Jim Pappas, director of Technology Initiatives, Intel Corp. “Cadence’s latest PHY and Controller IP demonstrate their commitment to PCIe 5.0 performance and interoperability with our 12th Gen Intel Core and 4th Gen Intel Xeon Scalable platforms.”

“As a long-standing PCI-SIG member, Cadence plays a role in the advancement of PCIe technology,” said Al Yanes, President and Chairperson of PCI-SIG. “By participating in the compliance program, Cadence is helping to further the continued adoption of the PCIe architecture.”

The Cadence IP for PCIe 5.0 architecture supports the company’s Intelligent System Design strategy, which enables advanced-node SoC design excellence. The PCIe 5.0 Design Kits for TSMC’s N7, N6 and N5 process technologies are available for licensing and delivery now. Cadence’s comprehensive portfolio of design IP solutions in the TSMC advanced processes also includes 112G, 56G, die-to-die (D2D) and advanced memory IP solutions.

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