Cadence's LPDDR5X memory IP solution consists of a silicon-proven PHY and controller designed to connect to LPDDR5X DRAM devices that follow the JEDEC JESD209-5B standard.
Gear Radio Electronics successfully taped out an LNA IC on the first pass by adopting Cadence and UMC certified mmWave reference flow.
The Cadence IP for GDDR6 is silicon proven on TSMC’s N5 process technology, exceeding Cadence's previous 16Gbps designs.
Cadence's Integrity 3D-IC platform has achieved certification for and met all reference design flow criteria for TSMC's 3DFabric offerings.
Keysight, Synopsys, and Ansys have developed a mmWave design reference flow for TSMC's 16nm FinFET Compact (16FFC) technology.
Synopsys' latest achievements in EDA and IP on the TSMC N3E process provide customers with robust solutions that help them meet the stringent power, performance and area targets for their designs.
TSMC has certified Cadence's digital and custom/analog design flows for the latest N4P and N3E processes.
Through the continued collaboration, the reference flow featuring the Cadence Integrity 3D-IC platform has been enabled to advance Samsung Foundry's 3D-IC methodology.
Cadence and Google Cloud are collaborating to accelerate system and semiconductor design with cloud-ready tools.