Cadence and Google Cloud are collaborating to accelerate system and semiconductor design with cloud-ready tools.
In response to software supply chain attacks, 73% of organizations surveyed say they have increased their efforts to secure their software supply chain.
The collaboration will enable designers to validate complex RF and mmWave design requirements for 5G/6G SoC and subsystem designs in the Synopsys Custom Design Family.
With Cadence Liberate MX Trio, Arm achieved the accuracy and capacity required to address advanced-node memory characterization challenges.
Cadence and Tower Semiconductor are collaborating to advance automotive and mobile IC development.
Siemens has expanded the early design verification functionalities of its Calibre platform for IC physical verification.
The 8nm RF design reference flow enhances time-to-results, quality-of-results and cost-of-results for next-generation RF design.
Cadence has expanded its Tensilica ConnX family with the debut of two new DSP IP cores for embedded processing in the automotive, consumer and industrial markets.
Cadence's PHY and Controller IP for PCIe 5.0 specification in the TSMC N7, N6 and N5 process technologies have passed certification tests.
Synopsys and Arm continue to deepen and broaden collaboration activities to accelerate time-to-market through highly optimized and silicon-ready system design and implementation solutions.