The consortium has chosen to use the PCI Express architecture as its first transport layer with additional higher speeds of 25Gbps and beyond.
Through close collaboration, members of the Cache Coherent Interconnect for Accelerators Consortium (CCIX) have aligned to a specification that addresses the need for data centre connectivity. The specification enhances the prevalent ecosystem to enable higher bandwidth, lower latency and full coherency, according to the consortium.
In addition, CCIX has chosen to use the PCI Express architecture as its first transport layer with additional higher speeds of 25Gbps and beyond. Using the PCI Express standard to transport the CCIX coherency protocol eases the implementation of CCIX in processors and accelerators. It also eases the deployment of CCIX technology in servers by leveraging the existing hardware and software infrastructure. Additional transport layers are expected to be added in the future.
The CCIX specification is available immediately to the consortium members. Initial products based on CCIX technology are expected in 2017.
CCIX allows processors based on different instruction set architectures to extend their cache coherency to accelerators, interconnect, and I/O. These highly capable accelerators become a key component in the processor system. The availability of the CCIX technology gives system designers the flexibility to choose the right combination of heterogeneous components from multiple vendors and address their specific system needs.
CCIX, formed in May and led by founding members AMD, ARM, Huawei, IBM, Mellanox Technologies, Qualcomm and Xilinx, recently welcomed 15 new members to the consortium.
The new members represent silicon providers and ecosystem partners in design, verification, software and systems. They include Amphenol, Arteris, Avery Design Systems, Atos Cadence Design Systems, Cavium, Integrated Device Technology, Keysight Technologies, Micron Technology, NetSpeed Systems, Red Hat, Synopsys, Teledyne LeCroy, Texas Instruments and TSMC.
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