Chiplet Ecosystem Gathering Momentum

Article By : Dylan McGrath

Momentum is gathering for the heterogeneous integration of chiplets from multiple vendors in a system-in-package

Momentum continues to coalesce slowly around the creation of an open chiplet ecosystem, enabling the heterogeneous integration of chiplets from multiple vendors in a system-in-package.

Chiplets represent one of several efforts to compensate for slowing performance gains through brute force scaling; it's the slowing of Moore's Law. While individual chip companies including Intel, Marvell, and startup zGlue — as well as system companies such as Cisco — have had some success in creating their own chiplet ecosystems, efforts to date have relied on proprietary multi-chip interfaces.

The development of an industry-wide open chiplet ecosystem that would allow designers to assemble "best of breed" chips incorporating components from multiple vendors requires not only standard open interfaces but also technology advancements in areas such as wafer testing and thermal management and the creation of new business models.

Steady — if slow — progress around an open chiplet ecosystem was on display last week at the second workshop of the Open Domain-Specific Architecture (ODSA) group, which now claims some 70 member companies and is working to define an open interface for chiplet-based design and seeks the creation of a stack-compliant interoperable chiplet marketplace. The ODSA operates under the umbrella of the Facebook-backed Open Compute Project.

According to Ramune Nagisetty, a senior principal engineer at Intel and director of process and product integration in Intel's CTO office, the need for chiplets is based on the emergence of new workloads combined with enabling advancements in architectures and packaging technologies.

Ramune Nagisetty

Ramune Nagisetty, a senior principal engineer and director or process and product integration at Intel, moderates a panel discussion at the ODSA workshop last week. (Source: Open Compute Project)

"The industry has reached an inflection point," said Ramune Nagisetty, a senior principal engineer at Intel and director of process and product integration in Intel's CTO office. "We have the opportunity to continue scaling package integration through the innovation of chiplets."

A year ago, Intel released its AIB protocol for its EMIB package as part of its work in a DARPA research program on chiplets. At the ODSA workshop last week, Intel followed that up by releasing version 5.2 of PHY Interface for PCI Express (PIPE), a stripped down version of the PCI Express interface that is described as a configurable short-reach PHY.

Meanwhile, the ODSA group continues to work on advancing its own open Bunch of Wires (BOW) physical layer interface. At the ODSA workshop, Bapi Vinnakota, an engineer at Netronome and the leader of the ODSA working group, actively recruited foundry and chiplet support for the BOW interface and introduced a new chiplet design exchange project to enable firms to make open chiplet physical descriptions that are normally kept confidential in machine readable form using a data-exchange format developed by zGlue.

"It's very difficult to share confidential information when you are working in an open organization," Vinnakota said.

Monolithic v chiplets

(Source: Open Compute Project)

The BOW interface was originally proposed during the ODSA's first workshop in March. The idea of BOW is to provide a common and simple parallel interface that operates at a relatively low data rate to enable chips in older nodes to be integrated into the system, such as integrating critical RF components advanced SiPs.

Growing Pains

Growing pains aside, the ODSA is making steady progress on the development of an open chiplet ecosystem. According to Nagisetty, what looks from the outside to be painfully slow progress actually mirrors the ramp common to other major technological inflection points, with the pieces coming together slowly first but then at a steadily accelerating rate.

"I think in the three-to-five-year timeframe, we will be looking at everything in a very different way," Nagisetty said in an interview with EE Times. "Things are starting, the ramp is slow, but it's going to increase in pace and as each standard and specification and tool falls into place, the rate of change will increase. I think in the three-to-five-year timeframe, this [chiplet-based design] is going to become more the rule and less the exception."

One cost-savings success story that many proponents of chiplet-based design point to is AMD's forthcoming 7-nm Epyc CPUs, which feature up to eight 7-nm processor dies linked with AMD’s Infinity fabric to a single 14-nm I/O chip with memory controller. The approach is an extension of the 14-nm Epyc that uses four dies on a single package.

"For us, chiplets are very real," said Gabriel Loh, an AMD Fellow who appeared in a panel discussion at the ODSA workshop. "It's something that we are building already, with the philosophy of getting different components on silicon regardless of their technology node."

ODSA Panel

Chiplet Design Experience Panel at the ODSA workshop. From left: Carlos Macian, eSilicon; Gabriel Loh, AMD; Dave Kehlet, Intel; Sanjeev Joshi, Cisco; Sagheer Ahmad, Xilinx (Source: Open Compute Project)

But while the concept of an open chiplet ecosystem has momentum and is progressing, it is not without its detractors or serious hurdles. From a technical standpoint, Nagisetty believes one of the most formidable hurdles to an open chiplet ecosystem involves testing — specifically being able to guarantee known good die prior to packaging, which will require very comprehensive content at wafer sort, and the ability to probe fine pitch bumps. The second major bucket of challenges Nagisetty sees involve thermal challenges driven by power, power density and thermal cross-talk.

But from a business model perspective, challenges are at least as vexing. Currently, the industry has certain types of business models associated with board-level components and others associated with monolithic SoCs. "But we are really just kind of beginning to understand the kind of business models needed when we combine silicon from different manufacturers," Nagisetty said.

For example: who brands the SiP device? Who markets it? And, of course, who is potentially liable if there is a security flaw?

"Who gets left holding the bag if it doesn't work?" Loh asked. He noted that there are some solutions in the industry that can be used as models. "The question is: how do you scale that?"

Packaging Yole

Another issue that surfaced during the panel discussion is that of margin stacking. If someone is assembling a "best of breed" device including chiplets from multiple chip firms, it's safe to assume that each chip firm will want to command high margins for its industry-leading silicon. Stacking all of these margins on top of one another could make the final product prohibitively expensive.

"All of these types of things have to be addressed," Nagisettyy said. So in certain respects, we're just starting on this path. We're learning a lot, and I think these things will eventually work themselves out through standards and specifications."


Nagisetty said the PIPE specification had its roots in the design of Intel's Kaby Lake G, the design that led to series of Intel Core processors that feature integrated AMD Radeon graphics cores, which use both PCI Express and EMIB to interconnect multiple chiplets made using different processes at different technology nodes.

"We learned a lot about how to integrate a component that was originally designed for the board and put it inside a package," Nagisetty said.

For Kaby Lake, Intel designers wanted to use PCI Express to connect the CPU to the Radeon GPU. But PCI Express is designed for driving signals long distances at high speeds and would have been too much power to place inside of the package. Instead, Intel designers came up with a scheme to tune the interface for the distance that the signal needs to travel, reducing active power by about 50% while also reducing the amount of time required for power state switching in the process, Nagisetty said.


PIPE V5.2 support for short-reach applications. (Source: Intel)

"We could save power and we could actually create a much simpler design at a lower cost design if we could take that PCI Express interface and really tune it down," Nagisetty said. The resulting PIPE specification not only enables designers to interconnect chiplets at a significant power reduction within a single package, but also gives them the flexibility to decide later in the design process whether some elements of their design are going to be board-level or package-level components, Nagisetty said.

In addition to Kaby Lake G, the the design of Intel's Stratix 10 FPGA — featuring silicon built by multiple foundries at multiple technology nodes in the same package — and Intel's Lakefield process — which incorporates Intel silicon at multiple technology nodes into the same package — gave Intel a lot of insight into how to string together chiplets from multiple sources, Nagisetty said.

"Basically you need to have interoperability supported by standards and specifications," she said, including not only the interface but material specifications to ensure that the different materials being used by different manufacturing facilities are compatible.

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