Due to the demand for more sophisticated applications, the design of systems-on-chip (SoC) is more and more complex.
Due to the demand for more sophisticated applications, the design of systems-on-chip (SoC) is more and more complex. Defacto Technologies, a French provider of design solutions at Register Transfer Level (RTL) level, has released what it calls a unified SoC integration platform that automates front-end tasks and allows to make decisions early in the design flow, thus saving time and reducing costs in the design process.
“Today, we need to build SoCs quickly with a maximum of automation taking into account several dimensions: design data (RTL or gate level), power intent, electronic system design (IP-XACT), register specifications, timing constraints, interface between hardware and software,” Chouki Aktouf, CEO of Defacto Technologies, told EE Times Europe.
How to capture all these dimensions in the SoC integration phase? Defacto said it has developed a common database which is structured so that different information (e.g. RTL, gate-level, UPF, LIB) can be read and taken into account before physically building the SoC. “With SoC Compiler, our goal is to help prepare the logic synthesis and compilation phases,” said Aktouf.
SoC Compiler is the ninth version of Defacto’s Star SoC integration solution.
SoC design has become a complex process requiring compartmentalization in sequential yet dependent steps. Hence the importance of unifying the design process and increasing automation.
Defacto claims SoC Compiler automates the front-end to take into consideration the physical constraints at an early stage of the design flow. For instance, Aktouf illustrated, “If I want to extract all the blocks that belong to the same power domain, I have to extract all the information related to the RTL, all the libraries that go with it and the power intent architecture that is expressed through the UPF. The solution must be able to fetch the right files, manage the consistency between the files to allow me to implement this order.”
SoC design projects almost always require customization. “If we need to add and execute custom verifications, the solution must allow them,” said Aktouf. “And as soon as we make a change, it should be automatically reflected and become visible on the whole flow.”
Today, several teams, often decentralized, contribute to the SoC design project. Any update or inconsistency detection must be visible to all of them. In real time.
“If there is a consistency problem, if I can’t move this block from one level of hierarchy to another because the UPF file doesn’t exist, the tool should raise a flag,” said Aktouf. SoC Compiler automatically evaluates the impact of each task on other tasks and identifies errors.
Defacto said SoC Compiler can be used with most scripting languages (Python, Perl, Tcl, etc.) and automatically translates commands into the more complex RTL code (VHDL, Verilog, System Verilog). For instance, “an engineer in India is in charge of an IP and is an expert in Tcl language,” Aktouf illustrated. “Another engineer in Silicon Valley works on another block and is an expert in Python language. The platform should allow them to express themselves as they wish.” APIs are essential to a heterogeneous, multi-site team.
SoC Compiler is built around 5 integrated tools to enable a unified and automated design flow: RTL designer, RTL IP integration, RTL Low Power, RTL DFT, and RTL Design Checker.
Time-to-market is a critical consideration, and a commonly used approach to shorten the design cycle is to reuse subsets of previous designs in new designs. SoC Compiler allows reuse of the code written for a project for another project. “If you have an old project, you can package from this old project IPs and subsystems automatically to share them and use them for new projects.” He continued, “This solution makes it possible to build the SoC before the synthesis and compilation phases, but also to package IPs and subsystems and thus maximize the reuse rate and reduce the cost.”
The design cycles of an SoC are limited in time and can’t be exceeded because the tape out has to go into production. More importantly, companies must be the first to hit the market to maximize their return on investment. The challenge is to maximize the power, performance, and area (PPA) for the most challenging designs within tight deadlines while keeping engineering costs under control. “Having a unified, multi-dimensional solution avoids iterations in the flow,” said Aktouf. “I start at the system level, work my way down, get to the physical level, come back on a second iteration, refine, and optimize. There are usually a large number of iterations, but we help to reduce this number.”
If, Aktouf illustrated, the experts at the physical level look at the layout and say ‘I know these two IP blocks need to be next to each other, but these ones need to be far apart,’ an analysis is done to understand what should be done at the architectural level given the routing and placement challenges.
“What we call the physically-aware SoC built or assembly is very important in order to reduce the effort, achieve higher PPA efficiency, thus better performance results,” said Aktouf.
Defacto said SoC Compiler integrates with existing EDA tool flows from all major vendors. It has been tested by companies such as OpenFive and Sipearl.
This article was originally published on EE Times Europe.