Designing Packaging for Modern Power-Conversion Applications

Article By : Maurizio Di Paolo Emilio

High-power devices and the packaging they require to perform.

Applications using renewable energy as well as other energy-saving technologies need dependable, compact and thermally efficient power sources. Devices with high power density, high switching frequency and the capacity to operate at severe temperatures and voltages are needed to promote innovation in wind turbines, smart grids, solar power systems, solar photovoltaics and electric-drive cars. Demanding power applications place stress on both the gadget and the box in which it is housed.

Despite silicon’s (Si’s) long-standing dominance in power applications, the need for higher efficiency and power density, as well as improved performance and lower prices, has led to a shift in power electronics toward wide-bandgap (WBG) semiconductors like silicon carbide (SiC) and gallium nitride (GaN). WBG devices have started to appear on the market recently, but their power-device package designs have not yet reached maturity, especially for high-temperature and high-voltage applications.

Thermal performance

Thermal performance has been one of the limiting factors for improving power density. Proper IC packaging is important for the heat to get out of the system easily. This allows the system to not see any temperature rises and these power losses can be affordable. The goal here is for thermal optimization of the IC packaging and printed-circuit boards (PCBs) to reduce the temperature rise in the presence of power-converter losses. The design trends to miniaturize the converter have made it difficult for system-level thermal designs with smaller silicon and package sizes. As the die area shrinks, the corresponding junction-to-ambient thermal resistance gets exponentially worse.

The power-electronic market requires increasingly smaller, more efficient and more reliable devices. Key factors to meet these stringent requirements are high power density (able to reduce both the footprint and the costs of the solution) and excellent thermal management (able to keep the device temperatures under control). The three main requirements of a thermal management system for power semiconductors are the following:

  • Heat shall be conducted from the device to the ambient environment with a thermal resistance low enough to prevent the junction temperature (TJ) from increasing beyond a specified limit. Due to the derating factor, TJ is usually lower than the datasheet value.
  • Electrical isolation between the power circuit and the ambient environment shall be provided.
  • Thermally-induced mechanical stress resulting from material coefficient of thermal expansion mismatch shall be absorbed.

The most common thermal management system for power devices is shown in Figure 1. It comprises a heatsink (which conveys the heat from the power semiconductor to the ambient environment) and an electrical insulator (thermal interface material) to separate the metal heatsink from the semiconductor junction. Because most dielectric materials have low thermal conductivity, there is a tradeoff between electrical isolation and thermal resistance.

Figure 1: Most common thermal management system for CSP GaN FETS (Source: EPC)

Thermal design

Designers must be aware of the advantages of WBG technology as well as the vital role that better thermal performance plays in attaining these significant objectives.

In modern SMD designs, the heat-conduction channel passes via the component’s legs and into the PCB, which is attached to a heatsink. The power components may be placed atop an insulated metal substrate (IMS) in demanding applications, which enhances thermal performance, as it is a better heat conductor than typical FR4 materials. However, bottom-side cooling (BSC) seems to be rather paradoxical, as heat tends to rise naturally.

Infineon Technologies has created top-side–cooled (TSC) discrete semiconductors and ICs via inventive packaging. In addition to using the heat’s natural upward movement, this idea offers a number of other advantages that are beneficial to the on-board charger (OBC) design and other related applications.

To dissipate heat in BSC, a cool plate or heatsink is often added to the bottom side of the PCB or IMS. As a result, placing components on one side is not possible, which results in a 2× reduction in power density. Additionally, the PCB and semiconductor devices are thermally connected, so they will function at the same temperature. Many WBG devices cannot be utilized to their full extent because the glass transition temperature of the FR4 PCB is lower than their operating temperature.

Figure 2: TSC permits double-sided component placement, allowing for a doubling of power density. (Source: Infineon Technologies)

With the cold plate bonded to the top side of the power components, these issues are easily addressed, allowing for components to be placed on both sides, and WBG devices can be used over their entire operating temperature range.

As IMS typically involves using a separate FR4 PCB for the driver and passive components, there can be a significant distance between the gate driver and the transistor that inevitably increases the parasitic effects that cause ringing, which is a very delicate topic when using WBG devices.

Figure 3: Double-sided components allow for short gate traces, eliminating the parasitics. (Source: Infineon Technologies)

As TSC allows all components to be placed on the same double-sided PCB, the driver can be placed directly below the corresponding transistor, eliminating parasitic effects due to the PCB. This enhances system performance and prolongs the lifetime of the MOSFET.

Multiple options exist for thermally bonding the transistor packages to the heatsink/cold plate. In general, the most straightforward approach is to place a single, thermally conductive gap-filler pad between the MOSFETs and heatsink. With a thickness of about 0.5 mm, this gives the best thermal performance, provided that any voids in the gap filler are addressed.

The gap filler is unreliable in ensuring enough electrical isolation between the transistors and the conductive heatsink in higher-voltage applications. In this case, 0.1 mm of thermally insulating material is positioned between the gap filler and the heatsink to ensure outstanding thermal performance while providing the necessary amount of electrical isolation.

The QDPAK (PG-HDSOP-22-1) devices from Infineon are designed particularly to profit from TSC. For various purposes, a range of features is available. For high degrees of controllability and full-load efficiency, a Kelvin source pin is offered. The symmetrical parallel lead architecture makes assembly and testing simple while also ensuring mechanical stability on the PCB.

SiC and GaN package options

The effectiveness of power conversion in electric cars is crucial for resolving issues about range and charging time. Because there is minimal improvement in passive component size at higher frequencies, the AC-output traction inverter seldom runs beyond 10 kHz to optimize efficiency. OBCs with massive magnetic components and a DC output, on the other hand, may benefit from smaller size and lower cost by switching at considerably higher frequencies. MOSFETs are often employed to prevent an increase in dynamic losses and a decrease in efficiency, while WBG devices made of SiC provide even lower losses.

Because of their fast switching and low-loss body diode, SiC FETs excel in hard-switching topologies, such as an OBC PFC front end, which is usually a totem-pole arrangement, or “active front end,” for high efficiency and bidirectional capability.

SiC FETs exhibit their best performance in high-voltage and multi-kilowatt applications, in which device dissipation may still exceed 10 W even with 99.5% or greater efficiency. The TO-247 package has gained popularity due to its very low junction-to-case thermal resistance, which helps to maintain an acceptable TJ increase. Advanced wafer-thinning methods and silver-sinter die attach are employed in SiC FETs to further enhance thermal performance. To prevent interference between the load current and the gate-drive loop, the bulk of Qorvo’s SiC FETs are offered in this configuration, often with a fourth lead acting as a Kelvin connection to the JFET source and marked T0247-4L. A TO-247 device will be manually fastened to an aluminum heatsink that is liquid-cooled using a ceramic insulator and thermal paste in OBC applications. Through-holes in a PCB with created strain relief on the leads will serve as the point of termination. While providing excellent thermal performance, this requires a lot of mechanical assembly, including clamping and soldering, many components and messy thermal paste application. There is also a restriction on the clearance between device pins and voltage isolation creepage.

Power engineers have recently focused heavily on GaN technology, particularly GaN-on-Si high-electron–mobility transistor (HEMT) technology. It clearly states that it will provide the high-power performance and switching at high frequencies that many applications need.

Numerous trends have addressed the market toward improvements in terms of RDS(on), improved switching figure of merit and reduced capacitances since the debut of cascode-mode technology in the leaded TO-247 package. Of course, GaN technology and operating mode are crucial, but as with any FET device, packaging is quite important. The constraints of conventional packages (TO-220/TO-247 and D2PAK-7) become more evident when the industry moves to higher switching frequencies. Copper-clip technology would enhance both electrical and thermal performance, allowing future high-voltage WBG semiconductors to really benefit from both electrical and thermal performance. To provide power GaN FET solutions the benefits of copper clip, Nexperia introduced the CCPAK package. CCPAK1212 has a footprint that is 10% smaller than the D2PAK-7, or about one-fifth (21.4%) the size of a TO-247 while permitting lower RDS(on) product.

The CCPAK delivers lower inductances than leaded packages because internal wire bonds are not present. Comparing CCPAK1212 and TO-247 at 100 MHz yields a total loop inductance of 2.37 nH, as opposed to almost 14 nH, as seen in the table in Figure 3. A thermal resistance of less than 0.5 K/W is one of the ultra-low package resistances that the copper-clip package also contributes to.


This article was originally published on EE Times.

Leave a comment