A better way to estimate breakdown voltage for ESD design windows

To ensure sufficient protection of integrated circuit (IC) design circuitry during an electrostatic discharge (ESD) event, IC chip designers must verify that ESD protection devices are properly implemented, and ESD discharge paths are efficient and robust. An ESD design window defines the voltage and current limits within which an ESD protection device operates during an ESD event. After selecting the type and size of an ESD protection device, designers know the operating and failing voltages and electrical current limits of the ESD protection device, but they must estimate the right-side boundary of the ESD design window, which is limited by the breakdown voltage of the victim circuitry. Using the Calibre PERC platform flow, designers can
quickly and accurately identify the electrical path between two given pins with the lowest total breakdown voltage, which can be used to accurately estimate the upper voltage limit of an ESD design window, ensuring adequate ESD protection for IC design circuitry.