Optimize layout vs. layout design comparisons for faster runtimes

Layout vs. layout (LVL) comparisons provide invaluable checkpoints throughout the system-on-chip (SoC) physical design implementation methodology. Frequent LVL checks enable designers to identify and review unintended changes between the current and reference databases early in the design flow, so they can prevent the costly re-work required when these changes aren’t found until later. Optimizing LVL performance for production flows using a comparison application like the Calibre FastXOR operation ensures these comparison iterations are fast and efficient, helping to shorten design and tapeout schedules.