IROC Technologies tapes out aerospace SoC with Aprisa place-and-route

Sponsor : Siemens
IROC Technologies tapes out aerospace SoC with Aprisa place-and-route

In this Case Study, Faced with a tight schedule and a demanding chip design, IROC turns to Siemens for a digital implementation flow.

Testing for the European Space Agency
For this project, ESA asked IROC to assess the suitability of Ultra Deep Submicron (UDSM) technology nodes below 22 nm for space applications. ESA requires high reliability in their chips and systems when faced with threats from the operating environment. For aerospace applications, one of the most important threats is single events (soft errors) caused by radiation at high altitudes and in cosmic space.

IROC’s challenge was to build an IC to act as the test vehicle for accurately measuring the reliability of an array of devices (such as standard cells, memories and IP) to measure the effect of single events or soft errors on those devices due to radiation at various altitudes. In addition to containing the structures to be measured, the chip needed to include the measuring circuitry itself, which should not be sensitive to the types of soft errors being evaluated. And, they had a tape-out deadline of three months.

IROC turns to Aprisa
IROC contacted the Aprisa team and they began working together to determine what software and support was needed for the project. IROC learned that Aprisa works well with third-party tools and also has excellent correlation to signoff tools.

Getting started with Aprisa, including installation, set up, and usage was easy. IROC was designing a new IC from scratch, with a new design flow, new design software, and a very tight schedule. For IROC, adopting the Aprisa software helped them reduce the risks so they could focus on meeting the tapeout schedule.

The Aprisa software is a detail-route-centric physical design platform for the modern SoC. Designers get excellent quality-of-results and fast runtimes. Aprisa helps designers avoid iterations, improves power/performance/area tradeoffs, and reduces time-to-closure by pulling detail-route visibility earlier in the flow.

On-time tapeout
IROC built a new digital design flow, installed and set up the tools, completed the design and reached tapeout in three months. The design was manufactured and underwent the battery of analyses to generate reliability data for ESA. Aprisa was key to IROC’s success because they were able to implement a powerful and flexible RTL-GDSII design flow that was easy to use, fast, technology ready, and with excellent correlation with sign-off to reduce iterations. For the IROC team, the strong support from the Siemens engineers further established their path to success in a way standard “hotline” support never could.

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