Fujitsu eyes architecture to rival quantum computers

Article By : Vivek Nanda

Fujitsu Labs and the University of Toronto are developing a computing architecture to tackle combinatorial optimisation problems.

Fujitsu Laboratories Ltd is collaborating with the University of Toronto to develop a computing architecture to tackle combinatorial optimisation problems. The architecture employs conventional semiconductor technology with flexible circuit configurations to allow it to handle a broader range of problems than current quantum computing can manage.

Tough decisions

Certain decisions need to be based on arriving at the most favourable set of parameters from an enormous number of possible combinations. Real-world examples of this include determining procedures for disaster recovery, optimising an investment portfolio and formulating economic policy.

For such combinatorial optimisation problems, as the number of elements involved increases, the number of possible combinations increases exponentially. To solve these problems quickly enough for any practical use, you would need a dramatic increase in computing performance.

While conventional processors offer flexibility by processing these problems using software, they cannot solve them quickly. Moreover, Fujitsu Labs claims that the miniaturization that has supported the improvements in computing performance over the last 50 years is nearing its limits (see Figure 1)

[FujitsuArchitecture Figure1 cr]
Figure 1: Limits of conventional computing. (Source: Fujitsu Laboratories)

Current quantum computers, on the other hand, use the hardware approach–they solve problems based on a physical phenomenon–but since only adjacent elements are able to come into contact, the range of problems they can solve is limited.

Fujitsu aims to meet this challenge with multiple computation circuits that run in parallel to perform the optimisation computations, while enabling scalability in terms of problem size and processing speed. The company has prototyped the architecture using FPGAs for the basic optimisation circuit–the smallest constituent element of the architecture and found the architecture capable of performing computations about 10,000 times faster than conventional processors running a conventional software process called "simulated annealing." By expanding the bit scale of this technology, it can be used to quickly solve computationally intensive combinatorial optimisation problems.

Next: Parallelisation, probabilistic acceleration boost speed »

Leave a comment