The rise of a new populism symbolised by the UK’s Brexit vote and the election of Donald Trump in the U.S. is the biggest wild card at the macro level. Analysts are still reeling from the twin surprises that analyst Matt Gertkin of BCA Research called a black swan of globalisation as indicated in the photo. The trend is less likely to play out again in elections this year in the Netherlands, France and Germany, he said. Italy is a bigger risk for leaving the European Union, given the influx of refugees there. He also predicted rising government spending that could fuel inflation in China and the U.S., where President-elect Trump is expected to run large deficits with infrastructure projects and tax cuts. The resulting market “favors small caps with less international exposure,” he said.

Smartphones will continue to grow through Gartner’s forecast period, but their share of the semiconductor pie will peak in 2017 at 25.4% and their overall amount of chip revenue will max out at $97.7 billion in 2018 as growth shifts to mid- and low-end models.

EUV resists also need a supply source. Yoshikazu Yamaguchi, general manager for JSR, believes that it can be based on a foundry model. Many companies could develop a range of resists and some could command a premium for refinements like the fine Dassai sake he holds. Semiconductor revenues could surge 7.2% this year after a tepid 2016, but 2019 could flat-line with a cyclical downturn in memory, according to Gartner’s chip forecast. A big push from Apple marketing its next iPhone on the handset’s 10th anniversary could give the second half of the year a boost.

Over the next five years, traditional growth drivers will slump as new ones emerge in expanding industrial, storage and automotive markets. Non-optical sensors (NOS) will continue to be a small but fast-growing product segment across automotive, IoT and mobile markets like in this chart, Gartner predicts. It expects that optoelectronic products, such as LEDs and image sensors for cars and smart cities, will be the second-fastest-growing product area as computer vision surges ahead. In his keynote, Patton listed six growth areas that many others also pointed to in talks — 5G, artificial intelligence, automotive, AR/VR, IoT and China.

PCs and ultramobiles will be flat this year. Growth will be slight through 2020, though the segment will continue to decline as a slice of the overall chip market. The capital equipment sector remains the segment under the most pressure. “Semiconductor cyclicality has moderated, but for capital equipment, it’s gotten worse and that’s a big threat to supply chain stability,” said G. Dan Hutcheson, president of VLSI Research, predicting that the sector will grow 8% to $58 billion this year.

In packaging, demand for 2.5 and 3D stacks have “picked up a lot” in the past year. The GlobalFoundries has smart interposers using 32nm to 22nm-deep trench wafers with decoupling capacitors that enable lower-voltage stacks ready for production at its Fishkill, NY, facility now. The same former IBM plant is in development of advanced stacks using three silicon photonics links. Such designs could someday pack much of the electronics for a 5G base station on a single component. Top challenges include providing accurate, yet low-cost, waveguide alignment and managing thermals.

Handel Jones also forecasted foundry growth by process node. This chart shows the rapid rise of the 7nm generation. The landscape will continue to be diverse, with as many as half of all chips still made in 28nm or older processes by 2025. Chip makers must now innovate in multiple directions at once in process and packing technologies, said Patton of GlobalFoundries. “The 64Mbit DRAM design team with Siemens was a good size, but nowhere near our current 7nm team size — I call it an extreme sport,” Patton said. “It takes program management to a whole new level to coordinate all of these activities and get resource prioritisation right,” he added.

Design costs at tomorrow’s 5nm node could be nearly triple the already steep level of today’s advanced 14nm/16nm processes, predicted Handel Jones of International Business Strategies. Designers will “need tremendous volumes of sales to make a return on investment,” he said in a talk. Scotten Jones agreed that design costs are “skyrocketing; it’s definitely a big problem.” Deep learning techniques could be applied to reduce software complexity, which represents nearly half of design costs, said Handel Jones.

EUV won’t be ready for high-volume manufacturing for another two to three years, said Patton, a prediction reflected in this road map created by resist maker JSR. When it comes, it could eliminate as many as 20 masks and cut 30 days off of cycle time, he said, noting that he will install two of the latest systems in his Malta, N.Y., fab this year. “EUV is about to happen and it’s about time,” said An Steegen of the Imec research institute, which has helped pioneer the technology for many years.

In the short-term, it's becoming a neck-and-neck race among chip makers, said Scotten Jones, president of IC Knowledge. In this chart, he showed his view that TSMC recently took the lead from Samsung, which took it from Intel last year. The x86 giant will retake the lead with its 10nm process early this year, with GlobalFoundries stealing it back with its 7nm node in 2018, he predicted.

The names of process nodes have become marketing tools that no longer refer to any physical dimension in chips, said Jones. He created this chart to show his view of how the rival processes compared using traditional metrics. Rumors are that Samsung’s 10nm yields are low and TSMC’s 10nm node beats it in density, Jones continued. However, Intel’s 10nm node is the densest of the group with yields rising significantly and the process being transferred to fabs in Israel. TSMC will ramp its 7nm node this year using similar pitches as in Intel’s 10nm process. GlobalFoundries’ 7nm node will come on in 2018 with tighter pitches and a 30% reduction in die cost, he said.

An Steegen surveyed major areas that still require significant development work. Today, seven 80W systems in the field ran more than 80% of the time over four weeks and a 125W upgrade is on the way, she said. Patton noted that an underlying issue is that almost everything absorbs EUV light, which must bounce through a maze of mirrors inside the system. Many options are still being developed to get resists at resolutions below a 3nm target with reasonable doses and low line-edge roughness. One possibility includes using separate resists for trenches and holes and another for lines and pillars. The last big obstacle is to reduce mask defects, mainly with a protective cover called a pellicle. “You need excellent transmission in the pellicle material with the spec today at 90% [or higher], and the pellicle must be thermally and mechanically stable to withstand the [future] 250W light source,” Steegen said. Researchers are experimenting with coating pellicles with carbon nanotubes to prevent materials from thinning under exposure. Once a pellicle is developed, the industry will need to set up a source of supply for it.