IBM researcher Veeresh Deshpande and his fellow scientists have demonstrated InGaAs/SiGe CMOS using processes for manufacturing on 300mm wafers.
The current technology chain is seeing a huge trade-off between power and performance, resulting in reduced battery life and energy challenges. But a team of Zurich-based IBM scientists believes the solution to these challenges lies in three words: scaling and new materials.
Recently, IBM researcher Veeresh Deshpande and his fellow scientists received the 2017 Compound Semiconductor Industry Innovation Award for their five-year research focusing on using high mobility materials into silicon CMOS technology to scale below 7nm.
Deshpande's team demonstrated an Indium gallium arsenide (InGaAs)/Silicon-germanium (SiGe) CMOS technology on Silicon (Si) substrate using processes suitable for high-volume manufacturing on 300mm wafers. InGaAs/SiGe hybrid integration is one of the main paths forward to enable the further improvement of the power/performance trade-off metrics for digital technologies beyond the 7nm node. Based on selective epitaxy, the team's approach yielded functional inverters and dense arrays of 6T-SRAMs the basic blocks of digital CMOS circuits.
"This novel technology is expected to enable 25% better performance with the same power consumption, or to double the battery life of mobile devices while maintaining their performance," said Dr. Lukas Czornomaz, one of the lead scientists focused on the research.
The team's work—a first-of-a-kind—was disclosed at the last VLSI Technology conference, IBM said. It concludes a series of key demonstrations for InGaAs/SiGe CMOS reported in multiple contributions and highlights for the last four years at IEDM meetings and VLSI Technology Symposia. Since many years the technological bottleneck is to demonstrate a path that enable simultaneously the growth of high-quality InGaAs crystals, the fabrication of high performance InGaAs field effect transistors “on-insulator” and their co-processing with SiGe devices all on a silicon substrate.
While a few approaches have been proposed, the IBM team’s work is the only one that reports basic building blocks of digital circuits at relevant dimensions and achieves a major milestone towards a manufacturable hybrid InGaAs/SiGe CMOS technology. It is based on three key features in a single technology: the selective growth of high quality InGaAs-on-Insulator regions, the fabrication of InGaAs finFETs with physical gate length Lg= 35 nm with good device characteristics and the processing of functional 6T-SRAM cells with a cell area ≈0.4µm2.
It highlights the potential of the IBM team's research as the method of choice to co-integrate InGaAs and SiGe MOSFETs for advanced CMOS technology, which, in turn, paves the way towards future low cost RF or photonic circuits based on a similar hybrid III-V silicon technologies.
In the future, the team will continue to support the development of the technology towards manufacturing and explore its application to integrated RF communication and integrated photonic devices with Si CMOS for future IoT technologies.
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