Intel Backed Startup to Optimize and Monitor Chips

Article By : Rick Merritt

A trio of former Mellanox execs raised $38 million from Intel and others for products that will monitor and optimize chips from design through use.

SAN JOSE, Calif. – Startup ProteanTecs snagged $38 million from investors including Intel to take chip reliability to a new level using machine learning. The company claims its products optimize and monitor chips from design through to their operation in the field, reducing design time and defects while increasing yields.

“We are creating visibility that didn’t exist in this industry before. We want to paint a high-resolution picture of what’s going on in the chip from many perspectives like a self-driving car that uses cameras, radar and lidar,” said Shai Cohen, a co-founder of Mellanox who left the company two years ago and founded the startup with two longtime colleagues.

ProteanTecs will sell a mix of tools, IP blocks and cloud services that can help improve yields, simplify sorting and testing chips and predict failures in the field. Two unnamed chip vendors have already tested their products, one with a commercial product and one in a sub-10nm node.

With the latest B-round funds, “we are building an applications-engineering team because we are ready to take the business to scale,” said Raanan Gewirtzman, chief business officer of the company. He expects to hire about a dozen engineers mainly in the U.S. before the end of the year.

The startup came out of stealth mode Monday and is not revealing details about what its products cost or how they work. For example, it is not saying what sort of machine learning it uses, although it did describe a training phase when its Proteus EDA tool is initially used at design time.

The products include three agents, some implemented as IP blocks that are compiled and synthesized at design time. One agent classifies design and process parameters as part of a learning phase, another agent checks margins, and a third checks operational metrics such as voltage and clock feeds.

The technique provides “a way to look at the manufacturing distribution and divide chips into families that behave similarly from a parametric point of view within, say one sigma,” and is not influenced by frequency or temperature conditions, said Cohen.

“Family attributes will help reduce defect parts per million by an order of magnitude…because the families define a small population…a one-sigma movement relative to the whole population looks like a seven-sigma movement in the family,” he said.

Chips can be queried by ProteanTecs’ cloud service to create graphs of their performance degradation “with high coverage” over time and anticipate failures, he added.

Protean Tecs

The startup will charge upfront licensing fees for its tools and IP as well as ongoing charges for access to its cloud services. It claims its capabilities will not impact chip area or performance.

ProteanTecs got its start amid discussions among Cohen and two colleagues who all left Mellanox at about the same time. The trio had worked together for nearly 20 years at the networking company and nearly a decade before that at Intel.

“The year after leaving Mellanox, Evelyn [Landman, ProteanTec’s CTO,] and I continued to work on some ideas for starting a company…I thought I could have some free time, but Evelyn was driving like hell,” Cohen said.

Both the ideas and their implementations were developed by the startup from scratch. The third co-founder is Roni Ashuri, former senior vice president of engineering at Mellanox.

The company is based in Israel and will use much of its latest round staffing up U.S. offices in and beyond Silicon Valley. Investors include Intel Capital, Mitsubishi UFJ Capital, and Avigdor Willenz, the founder of Annapurna Labs, acquired by Amazon. ProteanTecs has taken nearly $50 million in total investment to date.

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