Intel, RISC-V Groups Race to Develop Tomorrow’s Processors

Article By : Rick Merritt

Intel and RISC-V backers announced rival alliances to nurture competing ecosystems around tomorrow’s processors.

Intel initiated Compute Express Link (CXL), an open chip-to-chip interconnect that it expects to use on its processors starting in 2021 to link to accelerators and memories. Other members include Alibaba, Cisco, Dell EMC, Facebook, Google, HPE, Huawei, and Microsoft.

Separately, a handful of RISC-V proponents launched the CHIPS Alliance, a project of the Linux Foundation to develop a broad set of open-source IP blocks and tools for the instruction set architecture. Initial members include Esperanto, Google, SiFive, and Western Digital. CHIPS stands for Common Hardware for Interfaces, Processors, and Systems.

The CHIPS Alliance is, by far, the most ambitious of the two efforts and is just one of several open-hardware initiatives in the works at the Linux Foundation. CHIPS aims to create open-source blocks for a variety of embedded cores as well as multi-core SoCs capable of running Linux — and, ultimately, an open-source design flow to build and test them.

riscv cxl logos
CLX is ahead by a logo of the CHIPS Alliance, which has yet to hold its first formal meeting.

By contrast, the Intel-led CXL competes head-on with a similar group called CCIX, launched in 2016 by Arm, AMD, IBM, and Xilinx. Both groups will use PCI Express as the basis for interconnects to which they add cache coherency.

Intel claims that it was working on CXL for years and recently agreed with partners to open it. Its implementation claims to enable lower latency and less processing overhead on target devices than CCIX, but the CXL group provided no specific numbers.

CXL will start off using the 32-GT/s PCIe Gen 5, enabling PCIe I/O, cache-coherent processor links, and load/store memory semantics. Xilinx has already released one of the first chips using CCIX, initially based on today’s PCIe Gen 4.

“CCIX is a few years ahead, and there are silicon and systems being built with it,” said Gaurav Singh, a vice president at Xilinx who leads CCIX. “I expect this move by Intel to get a bunch of customers and developers who have been on the fence to jump onto available CCIX systems.”

CXL could be future Optane link

Fast interconnects are becoming increasingly important. Processors look to external accelerators and new memories to achieve performance gains as CMOS scaling slows.

Nvidia’s latest deep-learning systems use its proprietary NVLink to IBM Power 9 host processors. AMD designed its Infinity fabric to link its processors and GPUs, and IBM has its own OpenCAPI.

The emerging RISC-V community has an oar in this water. WD announced OmniXtend late last year, an open-source coherent interconnect based on an Ethernet PHY. The interconnect, along with the Swerv embedded core, will be WD’s initial contributions to the CHIPS Alliance.

All sides will compete for resources in a war of rival ecosystems.

“If AMD and others jump in, CXL could win,” or CCIX and CXL could merge, said Kevin Krewell, an analyst for Tirias Research. It’s too early to gauge the technical merits of CXL and how the rivalry will play out, he added.

CXL debuts as giant cloud providers in its membership are developing their own chips, including accelerators that will need to link to the Intel processors in their data centers. So far, the group lacks any other members making chips.

Jim Pappas, an Intel director of technology initiatives behind CXL, helped launch the original PCI and USB interfaces now used on nearly all computers. “PCI launched with just five promoters; this time, we have nine, and this is the most senior and influential group I’ve ever put together,” said Pappas, adding that Intel deliberately limited initial promoter-class members.

“We expect that competitors in CPUs, GPUs, FPGAs, and communications chips will get on the bandwagon,” he added. “We are used to working with competitors.”

Pappas would not say whether Intel will use CXL for Optane DIMMs as an open alternative to its current DDR-T protocol. However, he noted that CXL is optimized for persistent memory and will complement, but not replace, DDR.

A spokesman for Dell who leads the GenZ group said that the computer maker will use CXL inside its systems and GenZ as a link to external accelerator and storage systems.

CXL contributors pay $10,000 a year for royalty-free access to the spec. Adopters can join for free.

Group aims to assemble open-source design flow

The CHIPS Alliance aims to go beyond the work on the RISC-V ISA at the RISC-V Foundation to create a full library of open-source cores, blocks, and tools.

“As with Linux, we have seen RISC-V companies developing very similar IP elements like a lot of computer companies developed internal OSes to ship a service,” said Zvonimir Bandić, a Western Digital researcher who sits on the board of the RISC-V Foundation. “So the idea is to make common building blocks so we can focus on higher-value products.”

Members aim to find a balance between what they give away and sell.

“I expect my team to contribute a number of RISC-V cores smaller than Swerv and much bigger … We will open-source the cores but not the flash controller designs we use them in,” he said.

CHIPS also plans an umbrella project that, over a few years, will create and verify all the blocks needed for a multi-core RISC-V SoC that can run Linux. The work will be funded from membership fees that range from $25,000 to $2,500 a year. The blocks and tools will be available royalty-free under Apache and other licenses used by the Linux Foundation.

“Our ambition is to attract a very large number of members, at least the size of the RISC-V community,” Bandić said.

As their initial contributions, Google will submit a universal verification methodology for testing RISC-V chips, and SiFive will provide an unspecified design tool. Over the next decade, the group aims to assemble an entire open-source design flow for RISC-V.

The group’s initial focus will include leveraging existing open-source projects such as the Verilator simulator as well as some verification and synthesis tools. Some are being developed by universities as part of a DARPA project.

“There’s a lot of work going on to democratize silicon design,” said analyst Krewell. “The hard part is back-end verification. These people are idealistic and may underestimate the complexity of building a fully functional open-source chip and design flow.”

The alliance is the latest of about 175 projects at the Linux Foundation. The group has expanded from Linux in computers to its use in embedded systems from cars and consumer products to network gear and is now helping develop related spaces such as the Docker image format for containers.

“We will see future projects sharing data sets for AI,” and multiple projects are in the works for open-source hardware, said Michael Dolan, a vice president for strategic programs at the Linux Foundation.

At an event this week, the Linux Foundation aims to roll out a range of new high-level software projects with partners including Facebook, Google, and Netflix, among others.

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