The collaboration will enable designers to validate complex RF and mmWave design requirements for 5G/6G SoC and subsystem designs in the Synopsys Custom Design Family.
Keysight Technologies Inc. has extended its collaboration with Synopsys with the integration of PathWave RFIC Design (GoldenGate) with Synopsys Custom Compiler design environment and Synopsys PrimeSim circuit simulation solutions. This will enable designers to validate complex radio frequency (RF) and millimeter wave design requirements for 5G/6G system-on-chip (SoC) and subsystem designs in the Synopsys Custom Design Family.
“We are migrating our RF design environment to industry-leading commercial tools and workflows based on the Synopsys Custom Compiler™ design and layout solution,” said Koji Tomioka, vice president at Asahi Kasei Microdevices Corporation. “Keysight’s RFIC design tool integrated with Custom Compiler provides best-in-class layout and simulation capabilities to design and verify our millimeter-wave radar chips. We anticipate that the Synopsys-Keysight collaboration will save us time versus the maintenance of our in-house developed tools.”
The complexity of design requirements for radio frequency integrated circuits (RFICs) that are used for wireless data transmission, such as transceivers and RF front-end components, continues to grow. Next-generation wireless systems target a range of new capabilities including higher bandwidth, more connected devices, lower latency and better coverage. To address these requirements, designers need to simulate and measure RF performance to a greater level of accuracy.
The integration of PathWave RFIC Design (GoldenGate) simulation software, which models complex integrated circuits, with Synopsys Custom Compiler, part of the Synopsys Custom Design Family of products, addresses this challenge by enabling designers to achieve power and performance optimizations and efficiently deliver 5G and 6G designs.
“Native integration of Keysight’s PathWave RFIC Design (GoldenGate) with Synopsys’ Custom Compiler extends our collaboration to address end-to-end workflows for increasingly complex wireless designs,” said Niels Faché, vice president and general manager of Keysight’s PathWave Software Solutions. “This integration enables customers to access Harmonic Balance and Envelope simulation capabilities, as well as Keysight’s Virtual Test Benches, to reliably compute error vector magnitude and adjacent channel power ratio early in the chip design and verification process.”
Integration of Keysight’s PathWave RFIC Design (GoldenGate) into the Synopsys environment and Custom Compiler design workflow provides customers with an enterprise-grade solution for RF and wireless design, delivering benefits including complementary, high-capacity RFIC simulation solutions to validate complex SoCs with accurate electromagnetic (EM) models for RF and millimeter-wave design blocks; improved productivity with defined common testbenches, measurements, and simulation setup; and ability to meet complex RF and millimeter-wave design requirements to facilitate the creation of 5G and 6G SoC and subsystem designs.
“To enable key differentiating advantages for 5G/6G designs, Synopsys is delivering robust RF design solutions that deliver best-in-class design, simulation and layout productivity workflows,” said Aveek Sarkar, vice president of engineering at Synopsys. “As a result of our strong relationship with Keysight, our customers can now take advantage of the complementary RFIC simulation products within the Synopsys Custom Design Family. The custom design flow enables a more productive design and verification solution that delivers significantly faster layout and design closure, providing designers an accelerated path to meet their speed, bandwidth and data throughput requirements and time-to-market targets.”
This marks a continuation of Keysight’s strategic partnership with Synopsys, which recently integrated Keysight’s PathWave RFPro with the Synopsys Custom Compiler design environment, enabling customers to rapidly and accurately design wireless chips using TSMC’s N6RF Design Reference Flow