Micron stakes business on 3D NAND with new fab process

Article By : Kevin Gibb

Micron has taken an innovative approach to shrinking the die area by placing active circuitry under the NAND array.

Micron, the second chip vendor to commercialise 3D NAND, is taking an innovative approach to potentially reducing costs.

Micron has commenced production of its 32 layer (32L) 3D NAND flash memory, with the Crucial 750GB SATA 2.5in SSD being one of the first commercial downstream products containing the devices. The marketing literature for the SSD, shown in Figure 1, includes sequential read/write speeds of up to 530/510MB/s, respectively; a 90x improvement in energy consumption over typical hard disk drives (HDD), and the claim of increased durability.

The Crucial SSD is priced at about ₹13,415.62 ($200), making it an attractive option for laptops, and we are seeing more computers being spec’d with SSDs instead of HDDs. Hard disk drives (HDDs) might be on the way out, but they continue to show impressive technological improvements, and are still cheaper than SSDs. So we expect HDDs to continue to dominate sales for the near term.

__Figure 1:__ *Crucial CT750MX300SSD1 750GB SSD from Micron (Source: Teardown.com)*

The front and back circuit board pictures taken from the deep dive teardown report of the Crucial 750GB SSD are shown in Figure 2, and we see eight of the Micron NAND flash memory packages. This is twice the four 42L 3D NAND packages that we at TechInsights found in Samsung’s T3 2TB SSD, which contained Samsung's 48L 3D NAND. So from a package count perspective, Samsung has the lead on memory bits per package. Does this hold true at the die level?


Figure 2: Front and back circuit board pictures of Crucial SSD with Micron 3D NAND (Source: Teardown.com)

Samsung has managed to put 16 dies into each of their NAND packages, as shown in Figure 3. Doing some math shows each of the 99.8mm2 large dies having a 32GB capacity, or 320MB/mm2.

The Crucial 750GB SSD contains 8 Micron packages, with each package containing 2 dies that measure 165mm2 in area. This gives us 284MB/mm2 bit density, which is less than Samsung’s 320MB/mm2 bit density. But much of Samsung’s advantage comes from its 48L structure and its 20nm half bitline pitch, as compared to Micron’s more relaxed 40nm half bitline pitch.

Perhaps our comparison should be to Samsung’s earlier 32L V-NAND, released in 2014, also fabricated with a 20nm half bitline pitch. And here we find Micron’s 284MB/mm2 bit density to be quite favourable compared to Samsung’s 127MB/mm2 32L V-NAND bit density.

__Figure 3:__ *Samsung K9UGB8S7M 48L V-NAND Flash memory (Source: TechInsights)*

Figure 4 shows the Samsung 48L V-NAND die delayered to diffusion, and we can see two large NAND macros dividing the die in two. The page buffers and peripheral circuitry are below the NAND array macros. The array macros are filled with the source select transistors and source line contacts used by the vertical NAND strings.

__Figure 4:__ *Samsung 48L V-NAND diffusion level die photograph (Source: TechInsights)*

Micron’s diffusion level die photograph, seen in Figure 5, has quite a different layout, with 64 macros across most of the array. We have not analysed them yet, but we think that they contain the page buffers, row decoders, word line switches and perhaps miscellaneous "glue" logic. This is a very much different design strategy, and Micron has touted the placing of active circuitry under the memory arrays as a major factor in their increased bit density and reduced costing of their dies.

__Figure 5:__ *Micron 32L 3D NAND diffusion level die photograph (Source: TechInsights)*

Figure 6 is a SEM cross section taken through a portion of Micron’s 3D NAND die from TechInsights’ Structural Analysis Report. The vertical NAND string comprises 38 gate layers, 32 of which are for the NAND cells. The remaining 6 are likely being used as dummy and select gates. The NAND array that is stacked over 2 or 3 layers of metal interconnect and transistors. The metal 1 looks like it’s made of tungsten, which would suggest that might connect to the source select gates of the NAND array string. The metal 2 appears to be used for routing. Their exact roles will have to await the completion of our circuit analysis report on the device.

__Figure 6:__ *SEM cross section of the Micron 32L 3D NAND array (Source: TechInsights)*

The NAND cell structure is seen more clearly in Figure 7, and we have tentatively identified some of the layers, including the polysilicon annulus that runs in the vertical direction through the NAND stack. This annulus forms a vertical channel and it is surrounded by the floating and control gates. The floating gates are seen as the small dots that form a continuous ring around the central polysilicon channel. The control gates are separated from the floating gates by an interpoly dielectric.

__Figure 7:__ *SEM cross section of Micron’s NAND cells (Source: TechInsights)*

Samsung ushered in vertical NAND flash with its 32L V-NAND in 2014 and followed up with its 48L V-NAND in 2016. Micron is the second chip firm to commercialise 3D NAND and has taken an innovative approach to shrinking the die area by placing active circuitry under the NAND array. Micron has also fabricated the die using a larger process node (40nm half bitline pitch) that should reduce its manufacturing costs as compared to Samsung’s V-NAND product.

It is open to debate whether 3D NAND is cost competitive to planar NAND, but Samsung and Micron have decided to stake their businesses on 3D NAND. The question now is, can SK Hynix and Toshiba, who are also in the game, deliver a competitive product?

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