MIPS CPU takes the wheel in Mobileye’s autonomous car SoC

Article By : Julien Happich

The I6500 is designed to provide a highly scalable solution that can coherently implement optimised configurations of CPU cores within a cluster.

Mobileye is adopting Imagination's MIPS Warrior I-class I6500 CPU for its yet to come EyeQ 5 SoC for fully autonomous driving (FAD) vehicles.

A 64-bit multi-threaded, multi-core, multi-cluster design, the I6500 has been designed to provide a highly scalable solution which can coherently implement optimised configurations of CPU cores within a cluster (Heterogeneous Inside) as well as a variety of configurations of CPU clusters and GPU or accelerator clusters on a chip depending on the requirements of the system (Heterogeneous Outside).

In a single cluster, designers can optimise power consumption with the ability to configure each CPU with different combinations of threads, different cache sizes, different frequencies and even different voltage levels. Then, the latest MIPS Coherence Manager with an AMBA ACE interface to popular ACE coherent fabric solutions such as those from Arteris and Netspeed lets designers mix on a chip configurations of processing clusters–including PowerVR GPUs or other accelerators–for high system efficiency.

[Imagination MIPS block]
__Figure 1:__ *ACE Coherent Fabric (Source: Imagination Technologies)*

Based on a superscalar dual issue design implemented across generations of MIPS CPUs, Simultaneous Multi-threading (SMT) enables the execution of multiple instructions from multiple threads every clock cycle, providing higher utilisation and CPU efficiency.

Real time hardware virtualisation (VZ) allows designers to save costs by safely and securely consolidating multiple CPU cores with a single core, saving power where multiple cores are required, and dynamically and deterministically allocating CPU bandwidth per application. The combination of SMT with VZ in the I6500 offers “zero context switching” for applications requiring real-time response. This feature, alongside the provision of scratchpad memory, makes the I6500 suitable for applications which require deterministic code execution.

The I6500 CPU will be at the heart of heterogeneous coherent processing clusters in Mobileye’s next-generation EyeQ 5 SoC, which is designed to act as the central computer performing sensor fusion for FAD vehicles starting in 2020, Imagination stated as it announced the new CPU.

The EyeQ 5 will feature eight multi-threaded MIPS CPU cores coherently coupled with 18 cores of Mobileye’s Vision Processors (VPs). The VPs provide exceptional computing power within extremely low power budgets by combining Mobileye’s broad range of algorithms for mono/multi-camera driver assistance/autonomous systems, supported by its special vision accelerators and Imagination’s MIPS CPUs for ultra-efficient, real-time processing and control.

According to Elchanan Rushinek, SVP engineering at Mobileye, the new multi-threaded MIPS CPUs helped the start-up achieve over six-fold performance increases with each successive generation of EyeQ SoCs.

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