Mixel MIPI C-PHY/D-PHY Combo IP Now Available on TSMC N5 Process

Article By : Mixel Inc.

Mixel's MIPI C-PHY/D-PHY Combo IP is now available on TSMC’s N5 process.

Mixel Inc.’s MIPI C-PHY/D-PHY Combo IP is now available on TSMC’s N5 process. The MIPI C-PHY IP supports the v2.0 specification, and the MIPI D-PHY IP supports the MIPI D-PHY v2.5 specification.

Mixel’s MIPI C-PHY/D-PHY combo IP is a high-frequency, low-power, low-cost, physical layer. The MIPI C-PHY IP supports a speed of 4.5Gsps per trio, an equivalent data rate of 10.26Gbps/trio, and in MIPI D-PHY mode, the IP supports speeds up to 4.5Gbps per lane. With up to three trios in C-PHY and up to four lanes in D-PHY, the combo IP reaches an aggregate bandwidth of 30.78Gbps and 18Gbps in their respective modes.

There are multiple configurations of this combo IP available, including area optimized transmitters or receivers, supporting either the MIPI Camera Serial Interface 2 (CSI-2) or MIPI Display Serial Interface 2 (DSI-2) as well as a universal version of the IP which supports all configurations. In addition, Mixel also offers its patented RX+ and proprietary TX+ versions of its MIPI receiver and transmitter IPs. These unique configurations allow full-speed, in-system testing without the area penalty of a universal configuration and are designed for safety sensitive applications such as automotive, medical, and other use cases where safety and reliability are critical.

Mixel achieved first-time silicon success with the 5nm test chip and is now working on various configurations of the IP.

“Mixel is a valued contributing member and promoter of MIPI Alliance and its specifications for many years,” said Joel Huloux, MIPI Alliance chairman. “We are excited to see Mixel continuing to innovate and push the boundaries of MIPI by making its MIPI C-PHY/D-PHY IP available in the most advanced nodes.”

This combo IP, running at 4.5Gsps, was first announced in September 2020 on TSMC’s 22nm process.

“Mixel has been a long-standing partner of TSMC and has been delivering multiple generations and configurations of their MIPI IP for our mutual customers,” said Suk Lee, Vice President of Design Infrastructure Management Division at TSMC. “We will continue our collaboration with Mixel to enable next-generation silicon designs benefiting from the significant power and performance boost of our N5 process and help our customers quickly launch their new product innovations to market.”

Mixel was the first IP provider to silicon prove the first generation of MIPI C-PHY/D-PHY combo IP in 2016. Mixel’s MIPI PHY IP has been silicon-proven in 9 different processes at TSMC.

“We are excited to announce immediate availability of our silicon-proven MIPI PHY IP for TSMC’s 5nm technology, the most advanced foundry solution available today,” said Ashraf Takla, President and CEO of Mixel. “We have licensed this IP to multiple customers at this and adjacent nodes and continue to focus on expanding our portfolio in the most advanced processes.”


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