Moore’s Law Could Ride EUV for 10 More Years

Article By : Alan Patterson

ASML believes that advances in EUV technology could keep the industry on a trajectory of denser integration for perhaps another decade.

ASML plans to introduce new extreme ultraviolet (EUV) lithography equipment that will extend the longevity of Moore’s Law for at least ten years, according to executives at the world’s only supplier of the tools, which are crucial for the world’s most advanced silicon.

Starting in the first half of 2023, the company plans to offer customers equipment that takes EUV numerical aperture (NA) higher to 0.55 NA from the existing 0.33 NA. The company believes that the new equipment will help chip makers reach process nodes well beyond the current threshold (2nm) for at least another 10 years, according to ASML vice president Teun van Gogh, in an interview with EE Times.

“What we typically do is we try to make a tool available that can support our customers in a sort of two-year cadence,” van Gogh said. “When we start shipping high NA, which will be at the end of 2023, we will also have a two-year cadence there to support our customers. We believe that the technology that we offer will bring us well into the next decade to support our customers.”

The company expects that chip makers ramping up production with the new technology initially will use 0.55 NA for a cost-saving single-expose EUV process for advanced wafer layers, while using multi-pattern 0.33 NA along with older lithography technology for more mature nodes.  As the single-expose 0.55 NA technology reaches its limits, somewhere around six years from now, ASML predicts that chipmakers will once again resort to multi-patterning to reach even more advanced nodes with higher transistor densities.

The Dutch company is the world’s lone supplier of EUV equipment. In 2010, ASML shipped the first prototype EUV tool to an undisclosed Asian customer. Semiconductor production today is divided into the EUV “haves” like Taiwan Semiconductor Manufacturing Co. (TSMC), Samsung and Intel, which make advanced chips for customers like Apple, MediaTek and Qualcomm. The EUV “have not” chip makers years ago threw in the towel at leading nodes, jettisoning the associated multi-billion dollar capital expenditures and focusing on improved profits from legacy production lines and products that benefit little or none from process shrinks.

Have nots

Those EUV “have nots” include Chinese companies like Semiconductor Manufacturing International Corp. (SMIC) that last year were cut off from purchasing EUV tools when the U.S. government placed them on its Entity List in the midst of a growing technology war between the rival nations. The Chinese companies are not likely to gain permission from the U.S. government to buy ASML’s latest EUV tools, according to Mehdi Hosseini, an analyst with Susquehanna International Group, who covers ASML and TSMC.

“There will be no EUV shipments to any fab in China, including the multinationals that have fabs there,” Hosseini told EE Times.” Those multinationals with manufacturing in China include Samsung and Intel.

Outside China, only Intel, TSMC and Samsung will be able to use EUV for logic manufacturing. Samsung, SK Hynix and Micron will use EUV for DRAM applications, according to Hosseini.

ASML said that it has “no control” over restrictions on exports of its EUV equipment to China and that it abides by the laws and regulations of the countries where it operates.

The international Wassenaar Arrangement that was started during the Cold War governs the export of advanced technology that has “dual use” commercial and military purposes. The US has used the Wassenaar export restrictions to blunt China’s semiconductor expansion in recent years.

Obstacles at 3nm

In the next few years, ASML’s introduction of 0.55 NA tools will help leading semiconductor foundries like TSMC overcome obstacles they are now encountering at the 3nm chip process technology node, according to Hosseini.

“The only way foundries can do 3nm is to use EUV with multi patterning. This will certainly increase the wafer cost dramatically. The only way foundries can avoid EUV multi patterning is to use high NA (0.55 NA).”

Hosseini predicts that TSMC’s yet-to-be commercialized 3nm node will not make as big a splash as was once expected. At 3nm, the transistor density gains are “insufficient,“ with larger-than-expected interconnect pitch, making 3nm transistor cost similar to that at the current 4nm node with limited performance improvement, he notes.

In recognition of this stumbling block, the big-three chipmakers — TSMC, Samsung and Intel — have joined a race to be first with the new gate-all-around (GAA) FET technology at the 2nm node, according to Hosseini. One key technology shift for foundry leader TSMC will be in 3D chips, going from FinFET devices to new GAA FETs at the 3nm or 2nm nodes.

“We therefore expect a similar trend during the 2021-2024 period, with 3nm node smaller all while the three leading semiconductor manufacturers are racing to develop GAA transistor technology at 2nm, aimed at driving transistor density of greater than 220 million transistors per square millimeter with interconnect pitch of about 30nm,” Hosseini said in the research note.

Multi patterning

While multi patterning helps chip makers achieve higher transistor density, it also adds to production costs because of the increased steps in the chip making process and the high energy consumption of EUV with each scan.

“Of course, when you do multiple exposures, you multiply these steps,” Marco Pieters, ASML’s executive vice president of the EUV NXE business line, told EE Times. “If you look at all the steps that are needed to get to that final wafer, it is not just the litho effort and the energy by the litho tool, but also the deposition techniques.”

When EUV first became available with the introduction of 0.33 NA several years ago, ASML customers shifted from a multi-patterning technique using deep-ultraviolet (DUV) lithography to single-expose EUV, Pieters said. Yet, single-expose EUV is already reaching its limits.

“We see already trends that customers are starting to use EUV in a multi-patterning approach. The 0.33 NA will coexist with 0.55 NA, because for those layers where you only need single patterning with the current EUV, we think customers will continue to be using that technology in parallel to high NA.”

Companies making chips with EUV scanners are shifting to multi-patterning to squeeze more from the technology, according to Susquehanna analyst Hosseini.

“EUV multi patterning is the only way to migrate from 4nm to 3nm and eventually to 3nm+,” he says.

ASML still sees space for customers to mine new technology nodes from 0.33 NA EUV.

“We see a future where EUV 0.33 NA will be used for the next couple of nodes and even below what the industry calls 2nm,” Pieters says, noting differences in the way chip makers designate process nodes.

TSMC’s 5nm+, currently in volume production, is comparable to Intel’s 10nm SuperFin, also in volume production, according to Hosseini. Both nodes have densities of 175+ million transistors per square millimeter with interconnect pitch of less than 30nm, he said in the research report. Intel is hitting such targets using decade-old Immersion lithography while TSMC is already two years into adoption of EUV, according to the report.

Sole supplier

For EUV and high NA tools, ASML expects to remain the sole supplier for years to come.

“For the foreseeable future, we’ll be the only ones providing this technology,” Pieters said.

The transition to 0.55 NA from 0.33 NA EUV will be a simpler step for chip makers than the leap from DUV lithography to EUV several years ago, according to van Gogh. A supporting ecosystem of companies providing mask and resist technology has emerged, he said.

ASML declined to say whether more companies than the five current EUV adopters (Intel, Micron, Samsung, SK Hynix and TSMC) will invest in the new 0.55 NA tools when they become available.  Improving throughput will help to lower cost of ownership, according to ASML.

ASML’s current EUV equipment has increased from 125 to 170 silicon wafers per hour. The company says more than 200 wafers per hour is now achievable.

“By doing that, we try to basically improve the cost of ownership per wafer,” Pieters said. “We try to make sure that the litho cost of those systems actually will go down over time.”

Improving wafer throughput will be important for chip makers that are starting to do multi patterning with EUV, according to Hosseini.

An EUV with 200 wafers per hour (or higher) is needed for EUV multi patterning while high NA is still in development, he said.

Global megatrends and a “highly profitable and fiercely innovative ecosystem” will continue to drive semiconductor industry growth, according to ASML, adding that “increasing lithography intensity” is fueling demand for the company.

What could be better? ASML’s share price has tripled in the last three years.

This article was originally published on EE Times.

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