New chip architectures will drive semiconductors beyond what some see as a profound decline in Moore's law said CEOs of Arm, Micron and Xilinx.
Chief executives of Arm, Micron, and Xilinx gave diverging views on the outlook for Moore’s Law but shared enthusiasm for the future of semiconductors in a panel hosted by the Churchill Club in San Jose.
Moore’s Law has run out of gas, “and that is profound,” said Victor Peng, CEO of Xilinx, pointing to the rising costs of increasing performance and reducing power and area of chips.
“You can get one of the three, it’s hard to get two of three, and I would challenge anyone who says they can get three of the three,” he said. Today’s extreme ultraviolet (EUV) lithography systems only remove the complexity of multi-patterning today’s chips, the 7-5-3-nm names of the latest nodes “are all marketing numbers, and no one has fixed the interconnect problem.”
Arm chief executive Simon Segars generally agreed. “The cost of designing a 5-nm chip will be astronomical,” limiting the node’s use to a few companies who “can amortize it across multiple designs. Because of the constraints of Moore’s Law, you have to work harder — there’s no freebie in optical scaling anymore.”
Sanjay Mehrotra, CEO of Micron, took a more upbeat stance on the outlook for Moore’s Law in the memory sector. He foresees NAND stacks that exceed 200 layers and said that Micron has a roadmap of six DRAM processes ahead using traditional immersion steppers. “We wont use EUV until it is cost-effective in high-volume production.”
The slow decline of Moore’s Law has become a talking point for chip executives since 2013, when Henry Samueli said that Broadcom had been discussing it with its customers. Like others in the industry, Samueli also expressed optimism that engineers will leverage new architectures to drive performance gains.
Over the past year, Intel CTO Mike Mayberry has been giving talks that redefine Moore’s Law as anything that drives chip performance forward, arguing that Moore’s Law is alive and well. Emerging packaging techniques that the company described last week are a major lever that it and rivals including TSMC are using.
In the panel, Peng of Xilinx reiterated the view expressed in the landmark computing text by John Hennessy and Dave Patterson that tomorrow’s advances will come from architectures optimized for specific workloads. “The other trend is [that] you have computing [embedded] near storage and even connectivity will have intelligence in switches and programmability in the data plane.”
Mehrotra of Micron agreed, pointing to the 3D XPoint memory that his company co-developed with Intel. “Other disruptive memories will come along, and over the next several years, compute, memory, and storage [will be merged] on the same chip.”
“Innovation won’t dry up,” said Segars. Demands from a confluence of cloud computing, smartphones, IoT, 5G, and AI mean that “we will have to keep innovating at the semiconductor level.”
The rise of deep learning is ushering in a data-centric era in which “the way you develop software for embedded apps will change, extracting patterns in new ways and changing the way we think about solving problems,” said Segars. “It will take time for engineers to think about problems differently, not just writing linear code but using heterogeneous architectures.”