SAN JOSE, Calif. — If Naveed Sherwani gets his way, 2019 will be a year to remember for his startup, SiFive, the RISC-V architecture, and maybe even the whole semiconductor industry.

By the end of the year, SiFive could have cores that span the range of its entrenched rival Arm, said Sherwani, who in late 2017 was named CEO of the startup founded by RISC-V creators at Berkeley. This year, all RISC-V companies together could win more new sockets than Arm, he predicted.

The startup and the broader movement it is a part of are injecting new energy into a maturing chip sector. They are enabling more established companies to follow Apple’s lead in designing their own chips. And they are making it easier and cheaper for small startup teams to get into chip design.

“I’m seeing SiFive as more than an opportunity to make money; it’s an opportunity to revive the semiconductor industry, to bring new people into it,” he said.

“Nearly 4 million people view our videos, and that’s never happened in semiconductors,” he added. “So we have a chance to bring young people into this industry, and we need to get the next generation involved in semiconductors because without them, we are talking about the stagnation of the industry.”

Sherwani claims that SiFive has already attracted customers who are big systems OEMs designing their first chips. “System companies such as Whirlpool, Maytag, Tesla, Toshiba, and Daimler-Benz all want to go vertical,” he said.

Grand visions aside, Arm clearly has a more mature commercial offering than SiFive. In a recent talk, an Arm marketing manager noted that the company supplies about a dozen fundamental IP blocks that wrap around its cores. The cores are well-supported by foundries and top EDA vendors, and they have been tested to conform with a wide variety of industry standards and certifications.

The resulting platform costs more than cores from RISC-V rivals, but it provides a smoother, faster path to market, Arm contends. Partners such as Jon Masters, chief Arm architect at Red Hat, agree.

“Arm’s royalties pale in comparison to the amount of money it costs to tape out chips,” especially based on a free, open-source core, especially “the amount of money fixing it when something in the design goes wrong,” said Masters.

Nevertheless, the RISC-V ecosystem is growing and maturing quickly. Andes and Cortus already supply a range of RISC-V cores and tools.

“The number of new design wins for RISC-V in 2019 will exceed those for Arm … not revenue, just design wins,” said Sherwani, estimating that Arm lands 200 new sockets a year.

A 16-nm SoC template coming in 2019

While immature compared to Arm, SiFive is fleshing out its product offerings in both conventional and innovative ways.

“We have all the cores equivalent to Arm Cortex-M cores and will add embedded cores with vector processing in three months,” Sherwani promised. “By the end of the year, we will have both lower-end Cortex-A–level and high-end out-of-order cores — and next year, we’ll add specialized cores for AI and other customizations for cloud platforms.”

Beyond the cores, SiFive has announced one platform that Sherwani calls a template based on TSMC’s 28HPC node. It includes a cluster of four 64-bit cores and one 32-bit controller.

SiFive plans two more templates this year, at least one targeting the 16-nm node. The templates contain DDR memory controllers and other peripheral blocks, forming much of a full SoC.

Customers can access the templates in SiFive design tools hosted by Microsoft’s Azure cloud service. They can then pare back and modify the designs as needed. The startup promises that one of its engineers will verify the resulting design within 24 hours.

The offering is part of a promise that Sherwani made in April 2018 to collapse today’s chip design times from 18 months to as little as 20 days. Moving in that direction, it announced in October, it used its cloud service to design and tape out a Linux-capable, 1.4-GHz chip in six weeks.

“The whole process is not yet automated,” said Sherwani. “My goal is to get it down to a couple of weeks.”

Today, most of SiFve’s customers just buy IP. But in five years, he believes that as many as two-thirds of its customers will use its design tools to customize an SoC or hire SiFive to design SoCs for them.

Although the RISC-V instruction set architecture is open-source, most cores that SiFive provides are sold in a conventional way. However, the company aims to be flexible with licensing terms, offering cash-strapped startups, for example, access to IP without upfront fees.

SiFive’s licensing fees are lower than Arm’s, Sherwani contends, although neither company is public about its prices. Several rivals say that Arm has increased prices since it was acquired by SoftBank. Arm says that’s not true; however, it notes that its high-end cores such as the A76 always carry a premium.

“The switching costs for processor users is very high, so Arm can charge prices that reflect its dominant position — just shy of what would cause customers to switch away,” said Chris Rowen, a veteran of the chip IP sector.

“Much of the support of RISC-V comes from companies that want a real or apparent alternative to blunt Arm’s cost-aggressiveness,” he said. “Arm’s challenge is to figure out how to best walk the line — to maximize profitability while keeping defections low enough to sustain their strategic position. It’s a dangerous game.”