Chipmakers are turning to packaging to pick up some performance slack as traditional silicon scaling slows.
Engineers who design and build chip packages got the spotlight at Semicon West here. They usually labor in relative obscurity, but they’re on call now to help drive semiconductors down a road map splitting into more rivulets than the Mississippi Delta.
Moore’s law is approaching an economic end, delivering diminishing returns in the quest for smaller, cheaper, faster chips, speakers said. Packaging engineers are coming to the rescue with novel ways to stack individual chips into potent devices.
“Integration is the future,” said Bill Bottoms, a veteran engineering educator and entrepreneur overseeing work on a new roadmap for chip stacks. Estimated costs to design a traditional 5nm chip could soar as high as $600 million, and “this can’t continue,” he said.
Taking up the slack, engineers from Intel and TSMC and a government research effort showed packaging advances and the challenges ahead. They aspire to create a catalogue of chiplets that can be assembled like Lego parts, define standard interfaces for them, and drive their interconnects down to 10 microns and smaller.
Rahul Manepalli, director of module engineering at Intel, listed some of top challenges:
- Interconnects need to shrink to enable more than 250 I/Os per square millimeter.
- New materials are needed to enable higher signaling speeds and links that don’t warp under pressure.
- Standard sizes are needed for the glass and organic panels used in chip stacks.
- Packages need to adopt the kind of barrier layers currently used in fabs.
- Package makers need to adopt the rigorous process controls and automation techniques fabs use.
Eventually, “packaging will look more and more like the back end of the fab line using copper-to-copper links,” he said.
The recent spotlight on packaging “is exciting” said Manepalli who got his PhD in semiconductor packaging, then worked 20 years in the field at Intel. He helped design Intel’s embedded multi-die interconnect bridge (EMIB), its big commercial success in chip stacks to date.
Intel shipped more than a million devices so far using EMIB to create a bridge between FPGAs and serdes or PC processors and GPUs laying side by side. Ironically the work was originally aimed at smartphone SoCs.
Later this year, Intel will ship a notebook chip called Lakefield that uses another new chip stack technology called Foveros to link two chips face to face. By late 2020, the x86 giant aims to use the two techniques in tandem to create powerful stacks of stacks.
TSMC, DARPA weigh in on chip stacks
Like Intel, TSMC has a long-term vision of a combination of front-end and back-end fab techniques that could be used to create a variety of stacks of stacks covering any application. Building toward that goal, the Taiwan foundry has to date created an impressive lineup of at least eight novel packages for specific markets.
K.C. Yee, who manages packaging R&D at TSMC, walked through the current options. They span 2x reticle CoWoS (chip on wafer on substrate) chips it builds for companies such as Nvidia and Xilinx to svelte and cheaper smartphone options it makes for Apple and others.
The foundry has taped out more than 50 of the big CoWoS designs for customers in the five years the interposer technology has been on the market. Yee, 20-year veteran of packing technology, joined TSMC in 2011 just as it was ramping up work in chip stacks.
It likely will take years for giants such as Intel, TSMC and others to get to mature products and agree on common standards for them. Taking steps toward that goal, Andreas Olofsson is managing a U.S. government research project on chip stacks
“We’ve debated the pros and cons of serial vs. parallel links over the past 18 months,” said Olofsson. Ultimately, a government research project “is not the organization to drive a standard…we explore the tradeoffs, but we won’t set a standard — that has to come from industry,” he said.
Yet the group of nine companies and three universities is demonstrating progress. Intel released specs and a reference design for AIB, the physical-layer interface for EMIB. “Anyone interested in it can be up and running very quickly because it is very well documented,” Olofsson said.
This fall Intel will make a Stratix X FPGA with an EMIB link using 55-micron copper pillars to a 64GSample/second radar chip from Jariet. The work demonstrates “the cheapest way to create the most powerful radar chip,” Olofsson said.
In other projects under the program, UCLA has shown progress building 10-micron interconnects. And Lockheed Martin did an analysis of the types of chiplets it would need to serve its board designs.
Meanwhile an effort to publish an industry roadmap for chip stacks has released about ten chapters of work from its 21 technical working groups. The rest of the documents will be released before the end of the year, Bottoms said.
Next year, the group shifts into listening mode to take feedback from engineers in workshops around the globe. It will also start projects collaborating among its 21 teams.
The work “has already stimulated some pre-competitive collaborations and that will accelerate,” said Bottoms.
For example, one effort working with 200- and 300mm wafers found die with warpage of 1mm delivered acceptable yields but those approaching 5mm warpage did not. “We spent years putting that project together,” he said.
Bottoms predicted a big wave of tiny system-in package (SiP) devices is on the way. So far, the latest Apple Watch models are among the few examples of what’s to come.
Now most “major system companies have multiple SIPs in progress. You will see more of them this year and in two or three years, they will be everywhere,” he said.