SAN FRANCISCO — Toshiba Memory laid claim to the highest-capacity flash memory device, describing a 96-layer, 1.33-Tb 3D NAND chip in a paper at the International Solid-State Circuits Conference (ISSCC) here Tuesday.

The Toshiba device stores 4 bits per cell and achieves bit density of 8.5 Gb/mm2, more than 40% better than a 512-Gb TLC 3D NAND device also described at the ISSCC Tuesday by Toshiba and its partner in NAND development and manufacturing, Western Digital.

The device features a die size of 158.4 mm2. It utilizes a modified source-bias-negative-sense scheme, allowing for deep negative threshold voltage while maintaining a low supply voltage, according to Noboru Shibata, a Toshiba design engineer who presented the paper at ISSCC. The paper was authored by Shibata and a group of engineers from Toshiba and Western Digital.

The QLC Toshiba device also makes use of a modified two-step programming method, enabling it to realize a narrow threshold voltage for QLC with an 18% reduction in typical page programming time, according to the paper.

Toshiba memory Toshiba ISSCC 13.1: a 1.33-Tb 4-bit/cell 3D-flash memory on a 96-word-line-layer technology

In the other Toshiba-Western Digital paper presented in the same ISSCC non-volatile memory session, the authors — led by presenter Seungpil Lee of Western Digital — describe a 128-layer 3-bit-per-cell 3D NAND device that achieves 66-mm2 die size and 7.8-Gb/mm2 bit density.

The 128-layer device is enabled by three key technologies, including a four-plane architecture with circuit-under-array technology to improve performance per bit density, a multi-die peak-power management system to manage power consumption and improve write throughput, and a 4-KB page-read mode to reduce power consumption, according to the paper.

Toshiba Arch Perf Western Digital ISSCC 13.5: a 512-Gb 3-bit/cell 3D flash memory on 128-wordline-layer with 132-MB/s write performance featuring circuit-under-array technology