LPDDR3 DRAM memory controller’s IP core supports various power down modes, including ‘Deep Power Down.’
Catering to the industry needs for LPDDR memories, Arastu Systems’ LPDDR3 DRAM memory controller with LPDDR4 is optimised for FPGA and ASIC designs. It delivers increased performance at lower power consumption compared to its predecessors. The design IP supports the industry standard AHB/AXI, as well as can be made as per customer’s requirement.
The controller is fully compliant with JEDEC standard JESD209-3C and partner’s DFI PHY or DFI 3.1 PHY from any other vendor. The IP core supports various power down modes including ‘Deep Power Down’ which makes it suitable for smartphones, tablets, ultrabook, where performance is driven by increase in battery life. The core also supports multiple channels with a privilege to configure and manage each channel independently, and parameterised data width.
Arastu Systems also offers add-on cores such as ARM compatible interfaces, TRR, test/debug bus etc. which can be leveraged by customers based on their needs. Additionally, if required, the solution is also available in combo format with LPDDR3 and LPDDR4 single joint DRAM controller, which gives customers the flexibility to utilise either DRAM memory.