Microsemi has rolled the latest version of its Libero SoC software, the version 11.8, featuring a comprehensive suite of field programmable gate array (FPGA) design tools.

The Libero SoC tool suite includes the Mentor Graphics ModelSim Simulator, which allows line by line verification of hardware description language (HDL) code. Simulation can be performed at all levels: behavioural (pre-synthesis), structural (post-synthesis) and back-annotated, dynamic simulation. An easy-to-use graphical user interface enables quick identification and debug of problems.

While breakpoints have been used historically in embedded software, they can now be used to support FPGA logic debug functions. This increases productivity, usability and efficiency of FPGA designs, resulting in faster time to market for customers—particularly in the product validation phase, the longest cycle of product development, according to Microsemi. The SmartDebug enhancements complement existing debug capabilities which offer a new approach to debug FPGA devices’ status, memory and Serialiser/Deserialiser (SerDes) transceivers without using an integrated logic analyser (ILA).

Microsemi’s Libero SoC v11.8 is ideal for FPGA designs targeting applications within the aerospace, defence, security, communications, data centre, industrial and automotive markets. It now includes a number of additional compelling features, including a new netlist viewer providing visibility into different internal structures, new constraints management features offering block flow and an input/output (I/O) advisor, 20% runtime improvements for its SmartTime user interface and Windows 10 operating system support.

The Libero SoC v11.8 also comes with a new 60-day evaluation licence which can be used to evaluate Microsemi flash-based FPGA and SoC reference designs, tutorials and application notes, according to the company.

The Libero SoC v11.8 software toolset is now available for download from Microsemi’s website.