At the time PCI SIG started the 4.0 version it thought it might be its last copper-based chip-to-chip interconnect.
Chips using PCI Express 4.0 are heading to the fab even though the 16G transfers/second specification won’t be final until early next year. Once it gets all the details sorted out, the PCI Special Interest Group (PCI SIG) aims to start work in earnest on a 5.0 follow on running at either 25 or 32Gbit/s.
Cadence, PLDA and Synopsys demoed PCIe 4.0 physical-layer, controller, switch and other IP blocks at the PCI SIG’s annual developer’s conference. They showed working chips, boards and backplanes that included a 100Gbit/s Infiniband switch chip using PCIe 4.0.
It’s been more than six years since the PCI SIG ratified its last major standard, the 8GT/s PCIe 3.0. At the time it started the 4.0 version it thought it might be its last copper-based chip-to-chip interconnect. But since then Ethernet and Fibre Channel groups have pushed copper networking to 25 and 32Gbit/s respectively.
“We know we can take PCIe to the next generation, we just have to work out the details,” said Al Yanes, president of the PCI SIG in a press conference at the group’s annual developer’s conference here.
Figure 1: Cadence showed a Mellanox 100G Infiniband switch chip (left) linked to its controller (on the red board, right) using PCIe 4.0 across a backplane (centre). (Images: EE Times)
The questions about version 5.0 are many. They include determining if it will be backward compatible and still defined as a chip-to-chip link as all PCI standards have been to date.
“We can’t play the encoding trick,” said Yanes noting the version 3.0 adopted 128b/130b encoding up from 8b/10b previously used. “Using 256 coding won’t get you much more, so I don’t see many tricks besides increasing frequency” he added.
Demand will come from the usual suspects. Networking cards already hitting 100Gbit/s rates will need faster chip links as will next-generation graphics processors and solid-state drives.
It’s not easy creating a standard used in everything from smartphones to supercomputers for a member base of 732 companies. As data rates increased and signal margins narrowed, the time between new PCIe versions lengthened from three to seven years so far.
Figure 2: Mellanox's switch is among a handful of chips about to tape out with PCIe 4.0.
Getting PCIe 4.0 out the door
Figure 3: PLDA (Aix-en-Provence, France) showed a test board for PCIe 4.0 using its switch chip on an FPGA.
A version 0.7 of the PCIe 4.0 standard is currently being reviewed and is expected to be approved next month. Then engineers will put the spec through a wide range of lab tests to validate all features and their parameters before they sign off on a version 0.9. A close proofreading of that spec should lead to the 1.0 standard probably by April.
The group said a year ago that it hoped to finish the 0.7 draft, the last version to include any new features, at the end of 2015. “Trying to get everybody on board with a consensus took longer than anticipated,” said Yanes.
One of the last features approved was particularly thorny. Called channel modelling, it lets system engineers examine eye diagrams for each lane of the interconnect to see how much margin their designs have.
“The 4.0 spec has taken a long time. We have a number of customers taping out products using it in the fall because they figure the current 0.7 draft is good enough,” said Scott Knowlton, a senior product marketing manager in the IP group at Synopsys.
Figure 4: Cadence (above) and Synopsys showed the channel modelling feature of PCIe 4.0 running on their IP blocks in working silicon.
“We have one customer taping out a serdes device who felt they were waiting long enough and couldn’t miss their market window, so devices will come soon and compliance programs will come later,” said Arif Khan, a PCIe expert in the IP group at Cadence.
Earlier this year, IBM announced specs for its next server processor, Power9, including plans to support PCIe 4.0 in it.
The 4.0 spec trades off its faster data rates for slightly shorter distances of about 12-14 inches. Thus retimers and redrivers which became popular with version 3.0 likely will be even more widely used.
At the event, both Cadence and Synopsys demoed the channel modelling feature working in silicon based on their IP bocks. The Cadence chip was made in a 16nm FinFET process. Synopsys claimed its blocks reduced latency by up to 20 per cent and area by 15 per cent compared to prior PCIe blocks.
Figure 5: Pericom showed 12Gbit/s redrivers for PCIe it said cost a quarter as much as full retimers, but doesn't expect to have redrivers for the full 16Gbit/s spec for a year or two.