« Previously: Resistance scaling fixes PNR, signoff STA mismatch  

An increase in PNR WNS is expected and can be waved off as long as we meet the sign-off STA. In the case of design A, 10% resistance scaling helps in bringing down the WNS to -20ps, for which with PBA analysis we could meet the timing. In the case of design B, 10% resistance scaling did not give us good enough WNS so the resistance scaling is increased to 20%.

einfochips_resscale_04 (cr) Figure 1: Case studies using resistance factors to meet timing. (Source: eInfochips)

Impact of resistance scaling on other design parameters

When the tool tries to optimise a design with more constraints on the interconnect resistance, it will have an impact on other design parameters. Applying resistance scaling can have side effects on other design parameters, like shorts, DRCs and density. So when deciding how much pessimism we would like to introduce in PNR timing optimisation, we must consider other parameters. Using resistance scaling for less congested and lower density designs should be easier than a design with high congestion and density.

einfochips_resscale_05 (cr) Figure 2: Effect of resistance scaling (Source: eInfochips)

Finding the correct resistance scaling factor

Estimating a proper resistance scaling factor is the key activity in this methodology. Through trial and error, we can determine which number works best to meet timing without deviating much on other design parameters. We can compare the parasitic files (SPEF) from PNR and signoff extraction tools to find the proper correlation from previous designs, which could be more accurate.


Resistance scaling is a powerful tool for meeting timing demands, particularly when there is miscorrelation between PNR and signoff STA tools. But one must exercise care, as scaling can impact other design parameters.

First published by EDN.

« Previously: Resistance scaling fixes PNR, signoff STA mismatch