Synopsys VIP uses a native SystemVerilog/UVM architecture and features built-in comprehensive coverage and verification planning.
Synopsys has rolled out what it claims as the industry's first verification IP (VIP) and UVM source code test suite for Ethernet 200G.
As the requirements for increased bandwidth to support video-on-demand, social networking, and cloud services continue to grow, Synopsys VC VIP for Ethernet 200G enables system-on-chip (SoC) teams to design next-generation networking products with better ease of use and higher verification productivity, resulting in accelerated verification closure.
"Our Ethernet, Multilane-Gearbox (MLG) and FlexE products drive the latest high-speed communications and embedded system networking solutions," said Francois Balay, president of MorethanIP. "Synopsys' industry first 200G Ethernet VIP and source code test suite enable the verification process, for rapid introduction of MorethanIP 200G Ethernet high-speed communication IP Cores."
Synopsys VC VIP for 200G supports 4x50G or 8x25G line interface options with RS-FEC. Synopsys VIP uses a native SystemVerilog/Universal Verification Methodology (UVM) architecture and features built-in comprehensive coverage, verification planning, extensive protocol checks and protocol-aware debug. It features extensive and customisable frame generation and error injection capabilities, with additional source code UNH-IOL test suites also available. Synopsys VIP is also natively integrated with the Verdi Protocol Analyser debug solution for the highest debug productivity.
Synopsys VC VIP for Ethernet 200G and source code test suites are both in limited customer availability today.