RISC-V is heading for mobile. Qualcomm participated in SiFive's $65.4m funding round. We talked CEO Naveed Sherwani recently about the technology
Qualcomm Ventures is the newest investor in SiFive, the RISC-V processor IP startup. It’s a clear signal Qualcomm plans to exploit the potential of the RISC-V architecture in wireless and mobile. SiFive announced it raised $65.4 million in funding, with another $11m for its Chinese sister company SaiFan China.
SiFive also said it has achieved its 101st design win. The company is claiming it has significant traction in embedded markets as device manufacturers rapidly adopt domain-specific application processor designs to enable efficient computing in edge devices. It puts this down to the scalable capabilities of RISC-V that enable semiconductor companies to move through the selection, customization and enhancement phases of designs in just months.
The company had already raised $50.6 million in April 2018, though not all the investors from that round came in again on this latest round – notably Western Digital Capital, Samsung Venture Investment and Intel Capital. With the funding, SiFive wants to accelerate global expansion and technology development. In the past 18 months, it has grown from less than 40 employees to more than 400 employees across 15 locations globally in the US, India, China, South Korea and Taiwan. The Chinese subsidiary was established last year to serve the local market as an independent local entity, and is headed up by Thomas Xu, who until last year was CEO of Brite Semiconductor. Interest for SiFive’s technology in China is ramping up even faster than the US, according to the company, and SaiFan China already employs around 40 people there.
CEO: We Want to be a Silicon Company
We spoke to Naveed Sherwani, president and CEO of SiFive, while he was in Cambridge, UK, last month, presenting at one of the company’s 50 plus events it is conducting around the world this year, including in Israel, India, China, Pakistan, and several countries in the Far East, Middle East, South America and Australia.
He told us they just can’t hire enough people to deal with the leads the company is getting. “We have 450 people today, and we are hiring another 200-300 people right now. We’ve had around 600 companies contacting us, saying they are interested in doing something with us. I just don’t have people even to deal with them.”
Naveed Sherwani (Source: SiFive)
The company is expecting to do $100m in revenue this year, which breaks down into 75% from silicon, and 25% from IP licensing. The IP revenue comes from selling cloud licenses, which is taken mainly by larger customers. “Smaller and medium sized customers basically say, ‘build us this chip’; they either pay us US$1-4 million for NRE, or they buy silicon from us.”
Sherwani, who has been consistent with his story since I last met him at the GSA European Executive Forum in Munich in June 2018, said his vision is to make it easier for people to do chips, and reduce the expertise needed. “We want to become a silicon company. All the top semiconductor companies are exploring or using RISC-V, or they have already invested in us.”
He added, “It’s not my goal to sell by humans, because it cuts the innovation our clients can do. I really want to enable them, and the only way we can do that is to build the cloud delivery model where people can come and play and try and try again. Eventually, we just want to sell them a cloud license, and they can do whatever they want with it.”
He said there’s a real problem with the current IP licensing models out there. “Contracts should really be easy for the customer. For example, last month we closed a contract from a customer contacting us to delivering a core, within five days. This is a signed contract, not an evaluation license.”
“What I hate about the current IP system is this business negotiation, where if I want to change one core slightly or to another, I can’t without going through hoops. We want to make it completely easy.”
Talking about the cloud-based models from EDA vendors, he added, “I think current EDA vendors don’t know what to do with the cloud. They are trying to provision the licenses through the cloud. We do design in the cloud. That’s completely different.” Sherwani suggested that the EDA vendors were really just trying to sell licenses for seats accessible via the cloud, which means you have to use their tools on the EDA vendors’ servers via the cloud, which can be painfully slow and cumbersome.
“We don’t do that. We take your RTL, you log in to our servers, and you put that RTL onto our template. And the template is designed not by humans, but by automated flows on the cloud. If you look at our web interfaces, you don’t actually see the chip. Because we believe when you compile C code you don’t really want to see the assembly language, or the zeroes and ones that come out, since they tell you nothing if you look at them.”
“We want our customers to see, not even at Chisel level, but at a web interface level. Everything you get should be at that level. What happens at layout, what happens at verification, it’s our job. Today it’s not 100% automated. Even if it’s not fully automated, the chip we did with Microsoft still only took five weeks. But I think it will get towards 100% automation.”
Sherwani said that all the IP available in its DesignShare program sits inside the company’s templates which are hosted on an Azure server. “You are not sending your IP to somebody in China or India or anything like that. The IP leaves the IP vendor and goes to our cloud and just stays there. That way, clients never download that IP, or can download that IP, or even look at that IP.”
He uses an example. “We claim that if there is a USB or LPDDR in the design, you don’t have to become an expert on USB or LPDDR; it’s just there, all you have to do is use it. You don’t have to go negotiate a LPDDR contract with Cadence, then get it, then become an integration expert, then make a mistake. All you want to do is just have an LPDDR on your chip. So, the benefit of our templates is you don’t see the LPDDR. You actually don’t know it came from Cadence or somewhere else. It’s there and it works.”
We asked about licensees and applications for the company’s 101 design wins, and if there was any trend, but Sherwani said it is quite broad given that customers are not necessarily building high volume chips. He did give one example of a customer developing a smart real estate application, for which SiFive had done a working chip in just three months and would deliver 30 million chips to them next year if they are happy with the prototype. The company is the largest real estate owner in the world and is looking to use to its 40 million square meters of real estate in a better way, installing cameras and sensors to make better use of existing real estate.
Sherwani comes over as very passionate about democratizing the process of chip design and is spending a lot of resources evangelizing the story with the company’s travelling roadshow around the world, even into Africa. He believes that you need to enable the masses to innovate and that customization is the only way to achieve the performance.
The SiFive Portfolio
SiFive’s RISC-V core IP portfolio of 7, 5, 3 and 2-series cores scale RISC-V designs at several performance levels, from the 8-stage, dual-issue superscalar pipeline processor cores down to power and area optimized 2-stage, single-issue pipeline cores. It has 32-bit embedded cores for microcontrollers, edge computing and IoT devices, and 64-bit embedded cores for storage, augmented reality (AR), virtual reality (VR) and machine learning.
The configurable core IP is delivered via its online core configurator, the Core Designer. By adopting a native cloud licensing model for core IP evaluation, customization and RTL delivery, the company claims customers gain several advantages, such as ongoing maintenance. For example, the 7 series core increased performance from 4.9 to 5.1 in the CoreMark benchmark, due to ongoing performance optimizations since its launch.
The company also launched SoC templates in partnership with QuickLogic. These Freedom Aware templates are optimized for low power solutions in consumer and industrial IoT applications. It claims that using the templates, silicon designers are able to reduce design cycles to just a few months, decrease the total cost to first silicon by an order of magnitude and provide custom silicon solutions while removing the dependency on large semiconductor design teams.