RISC-V: A Boon for Military and Aerospace

Article By : Hailey Lynne McKeefry

RISC-V is getting attention from just about every vertical market, but it offers a number of particular benefits for military/aerospace designers.

The RISC-V Instruction Set Architecture (ISA), and open hardware standards in general, have the potential to be a real boon for military and aerospace designers. “RISC-V is being received with open arms by the military and aerospace sectors,” said Tim Morin, director of strategic marketing in Microchip Technnology’s FPGA business unit. “They are very excited about it.”

From a design perspective, the ISA addresses the need to minimize power consumption, streamline bill of material (BOM) costs, and optimize board space. “With RISC-V, when you create an integrated circuit, you do exactly what you need,” said Michael Cave, senior director, strategic technology at SiFive, adding that the company is bidding on DARPA projects currently. “The government loves that reality. The government feels like if they don’t do something innovative, China is going to capture the lead.”

Image courtesy: Microchip

Further, RISC-V offers the ability for government customers to inspect integrated circuits at the register-transfer level (RTL). “There are agencies that require that they can inspect the chips that go into certain classified applications,” said Microchip’s Morin. “If you don’t know what’s in it, you don’t get a grade.” Microchip is the number one supplier to the Department of Defense (DoD), he added.

Further, aerospace and defense electronics companies are interested in doing real-time in Linux, said Morin. Late last year, Microchip Technology, via its Microsemi Corp. subsidiary, announced the architecture for a new class of SoC FPGAs that combine the PolarFire FPGA family with a complete microprocessor subsystem based on the open, royalty-free RISC-V ISA. “The architecture brings real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core coherent central processing unit (CPU) cluster,” the company said. “The PolarFire SoC architecture, developed in collaboration with SiFive, features a f 2 MB L2 memory subsystem that can be configured as a cache, scratchpad or a direct access memory.”

These early developments are promising. “RISC-V is going to be a very important to aerospace and defense over the next 40 or 50 years,” Morin said.

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