RISC-V Boots Linux at SiFive

Article By : Rick Merritt, EE Times

Startup SiFive has taped out and started licensing a version of the RISC-V core that runs Linux, expanding its set of target markets.

SAN JOSE, Calif. — SiFive has taped out and started licensing its U54-MC Coreplex, its first RISC-V IP designed to run Linux. The design lags the performance of a comparable ARM Cortex-A53 but shows progress creating a commercial market for the open-source instruction set architecture.

A single 64-bit U54 core delivers 1.7 DMIPS/MHz or 2.75 CoreMark/MHz at 1.5 GHz. It measures 0.234 mm2 including its integrated 32+32KB L1 cache in a TSMC 28HPC process using a 12-track library.

A quad-core complex with a 2-MByte shared coherent L2 cache, Gbit Ethernet and DDR3/4 controllers and other peripherals measures ~30 mm2. SiFive will deliver a quad-core chip that includes an E51 management core that will ship in the first quarter on boards targeting software developers.

The single-issue, in-order U54 is expected to lag the performance of ARM’s dual-issue A53. By comparison, in late 2014 Freescale (now NXP) announced the QorIQ LS1043A, a midrange quad-core A53 running at 1.5 GHz delivering more than 16,000 CoreMarks at 6 W.

SiFive believes its part will be competitive in power and area efficiency. It also aims to innovate in its business model.

The startup will offer designers 100 prototype SoCs for $100,000 with no fees on third-party IP bundled with its cores until customers ship their chips. “Today, you pay all the IP costs upfront — we think that’s the wrong way,” said Jack Kang, vice president of business development for SiFive.

It’s still early days for RISC-V vendors and users.

Microsemi and Arduino are SiFive’s only announced customers. The startup claims that it already has multiple licensees of the U54, including military contractors and large semiconductor companies that serve markets including set-top boxes and data center accelerators.

Its existing 32- and 64-bit embedded cores have multiple licensees in areas including wearables and storage controllers. Several large chip makers are still evaluating RISC-V for potential use in multiple projects, said Kang.

For its part, Microsemi uses RISC-V as the PolarFire soft core in its FPGAs. The open source ISA offers lower cost and greater trust given its inspectable RTL, said Bruce Weyer, vice president of Microsemi’s programmable solutions group. He believes those advantages and others will help RISC-V proliferate, but it will take time.

“We’ve seen rapid adoption of RISC-V in MCUs but there’s a different maturity level in Linux,” Weyer said.

The standard U54-MC Coreplex contains four U54 cores and a single E51, but SiFive will license other configurations. (Image: SiFive)

The standard U54-MC Coreplex contains four U54 cores and a single E51, but SiFive will license other configurations. (Image: SiFive)

Processor IP vendors Andes and Cortus announced plans for RISC-V compliant cores earlier this year. The relatively small players are expected to eventually transition to the open-source architecture.

“It’s hard to put your finger on big market success for RISC-V yet because it’s too early to see SoC and systems shipments,” said Linley Gwennap, principal of market watcher The Linley Group (Mountain View, California).

“SiFive is certainly making good progress, and with the U54, it can now go after a broader range of embedded designs. The previous products were limited to use with an RTOS or other microcontroller-like designs.”

As for vendor support, “there’s been a surprising amount of work on RISC-V Linux systems to date using simulators and emulators,” said Kang. “Getting silicon will help spur the software ecosystem.”

UltraSoC recently joined Rambus as a member of SiFive’s third-party IP program called DesignShare, providing trace and debug tools and SoC monitors. SiFive aims to announce several more IP partners before the end of the year.

Separately, engineers hope to define a vector version of the RISC-V instruction set by the end of the year, targeting applications such as machine learning. A hypervisor mode is also in the works to enable virtual machines on RISC-V.

— Rick Merritt, Silicon Valley Bureau Chief, EE Times Circle me on Google+

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