Samsung certifies Cadence tools for 10nm process
Article By : Cadence Design Systems
The Innovus Implementation System enables larger designs and reduced turnaround time while supporting Samsung’s 10LPP design requirement.
Samsung Electronics has certified Cadence Design Systems' complete suite of digital and signoff tools for its process design kit (PDK) and foundation library on the company's second-generation 10nm low power plus (LPP) process.
Samsung, which has recently certified a design platform from Synopsys, has also validated the Cadence reference flow using a quad-core design with the ARM Cortex-A53 processor on the 10LPP process, which was implemented with the low-power design methodology covering power-gating and memory retention, IEEE 1801 UPF2.1 power intent, and statistical on-chip variation (SOCV)-based timing closure using the Liberty Variation Format (LVF) library.
The Cadence signoff tools that have been certified for tape-out using Samsung’s certification criteria for baseline accuracy include the Innovus Implementation System, which enables larger designs and reduced turnaround time while supporting Samsung’s 10LPP design requirements, such as floorplanning, placement and routing with integrated colour-/pin-access /variability-aware timing closure and clock tree and power optimisation.
Also certified is Genus Synthesis Solution, which delivers improved productivity during register-transfer level (RTL) design and highly correlated, optimal quality of results (QoR) in final implementation. The Quantus QRC Extraction Solution offers best-in-class accuracy versus foundry baseline; faster, scalable cell-level and transistor-level extraction; multi-patterning; multi-colouring; and a built-in 3D extraction capability, Quantus Field Solver (FS).
There's also the Conformal Logic Equivalence Checking (LEC), which ensures the correctness of logic changes and engineering change orders (ECOs) as well as the implementation flow, while enabling the comparison of different views/abstraction levels. The Conformal Low Power enables the creation and validation of power intent in context of the design, combining low-power equivalence checking with structural and functional checks to allow full-chip verification of power-efficient designs.
The Tempus Timing Signoff Solution provides integrated, advanced process delay calculation and static timing analysis (STA) that achieves Samsung’s accuracy requirements, including those at low voltage operation, while the Voltus IC Power Integrity Solution is a cell-level power integrity tool that supports comprehensive electromigration and IR drop (EM/IR) design rules and requirements while providing full-chip system-on-chip (SoC) power signoff accuracy.
Cadence's Physical Verification System includes advanced technologies and rule decks to support design rule checking (DRC), layout versus schematic (LVS), smart metal fill, yield scoring, voltage-dependent checks and in-design signoff, while its Litho Physical Analyser enables designers to detect and automatically repair process hotspots to improve design manufacturability and yield of digital, custom and mixed-signal designs, libraries and IP. This is part of Samsung’s foundry DFM offering.
The Cadence CMP Predictor, a part of Samsung foundry's DFM offering, predicts the 3D topology variation and hotspots caused by chemical mechanical polishing (CMP) to improve design manufacturability and reduce topology variation. The LDE Electrical Analyser allows layout-dependent effect- (LDE-) aware re-simulation, layout analysis, matching constraint checking, reporting on LDE contributions and the generation of fixing guidelines from partial layout to accelerate analog design convergence.
Rounding up the list is Cadence's Modus test solution, which provides scan and logic/memory built-in self-test (BIST) insertion, combined with a new physically aware 2D Elastic Compression architecture, enabling design engineers to achieve reductions in test time to minimise production test cost.
